From mboxrd@z Thu Jan 1 00:00:00 1970 From: swarren@wwwdotorg.org (Stephen Warren) Date: Thu, 23 Aug 2012 11:49:31 -0600 Subject: [PATCH 05/14] ARM: at91: add pinctrl support In-Reply-To: References: <20120810124820.GA20557@game.jcrosoft.org> <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com> <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com> <5034FC18.2090400@wwwdotorg.org> Message-ID: <50366D2B.4010807@wwwdotorg.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08/23/2012 01:06 AM, Richard Genoud wrote: > 2012/8/22 Stephen Warren : >>>> +Required properties for iomux controller: >>>> +- compatible: "atmel,at91rm9200-pinctrl" >>>> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be >>>> + configured in this periph mode. All the periph and bank need to be describe. >>> >>> Can you please be more elaborate on this mux-mask, like what each bit >>> means and why the bits are arranged like that and what it means on the >>> AT91 platform.... I was first reading the .dts and was like ?woot? so >>> I go to the bindings doc and I read this and I'm still like ?woot?.. >> >> Yes, I'm a little confused what this is, and wouldn't have a clue how to >> fill it in. > > With a practical example it's easier to understand. > Take a SAM9X5 release manual (here is sam9g35): > http://www.atmel.com/Images/doc11053.pdf page 11 (?4.3 package pinout) > in the file arch/arm/boot/dts/at91sam9x5.dtsi you've got the the > atmel,mux-mask like that: > > /* periphA periphB periphC */ > 0xffffffff 0xffe0399f 0xc000001c /* pioA */ > 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */ > 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ > 0x003fffff 0x003f8000 0x00000000 /* pioD */ > > Let's take the PioA - peripheral B: 0xffe0399f > From the documentation table 4-3, we can extract the column PIO > Periperal B for all signals PA0-PA31: ... > Each time it's possible to mux a pin to the peripheral B function (ie > when there's no "-----") the corresponding bit is set: ... > => this gives 0x399f Ah OK. It would be a good idea to briefly describe this process in the binding document I think. I assume this property exists to avoid the kernel driver having to contain tables for each Atmel device; the driver is generic. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH 05/14] ARM: at91: add pinctrl support Date: Thu, 23 Aug 2012 11:49:31 -0600 Message-ID: <50366D2B.4010807@wwwdotorg.org> References: <20120810124820.GA20557@game.jcrosoft.org> <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com> <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com> <5034FC18.2090400@wwwdotorg.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Richard Genoud Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org T24gMDgvMjMvMjAxMiAwMTowNiBBTSwgUmljaGFyZCBHZW5vdWQgd3JvdGU6Cj4gMjAxMi84LzIy IFN0ZXBoZW4gV2FycmVuIDxzd2FycmVuQHd3d2RvdG9yZy5vcmc+Ogo+Pj4+ICtSZXF1aXJlZCBw cm9wZXJ0aWVzIGZvciBpb211eCBjb250cm9sbGVyOgo+Pj4+ICstIGNvbXBhdGlibGU6ICJhdG1l bCxhdDkxcm05MjAwLXBpbmN0cmwiCj4+Pj4gKy0gYXRtZWwsbXV4LW1hc2s6IGFycmF5IG9mIG1h c2sgKHBlcmlwaCBwZXIgYmFuaykgdG8gZGVzY3JpYmUgaWYgYSBwaW4gY2FuIGJlCj4+Pj4gKyAg Y29uZmlndXJlZCBpbiB0aGlzIHBlcmlwaCBtb2RlLiBBbGwgdGhlIHBlcmlwaCBhbmQgYmFuayBu ZWVkIHRvIGJlIGRlc2NyaWJlLgo+Pj4KPj4+IENhbiB5b3UgcGxlYXNlIGJlIG1vcmUgZWxhYm9y YXRlIG9uIHRoaXMgbXV4LW1hc2ssIGxpa2Ugd2hhdCBlYWNoIGJpdAo+Pj4gbWVhbnMgYW5kIHdo eSB0aGUgYml0cyBhcmUgYXJyYW5nZWQgbGlrZSB0aGF0IGFuZCB3aGF0IGl0IG1lYW5zIG9uIHRo ZQo+Pj4gQVQ5MSBwbGF0Zm9ybS4uLi4gSSB3YXMgZmlyc3QgcmVhZGluZyB0aGUgLmR0cyBhbmQg d2FzIGxpa2UgP3dvb3Q/IHNvCj4+PiBJIGdvIHRvIHRoZSBiaW5kaW5ncyBkb2MgYW5kIEkgcmVh ZCB0aGlzIGFuZCBJJ20gc3RpbGwgbGlrZSA/d29vdD8uLgo+Pgo+PiBZZXMsIEknbSBhIGxpdHRs ZSBjb25mdXNlZCB3aGF0IHRoaXMgaXMsIGFuZCB3b3VsZG4ndCBoYXZlIGEgY2x1ZSBob3cgdG8K Pj4gZmlsbCBpdCBpbi4KPgo+IFdpdGggYSBwcmFjdGljYWwgZXhhbXBsZSBpdCdzIGVhc2llciB0 byB1bmRlcnN0YW5kLgo+IFRha2UgYSBTQU05WDUgcmVsZWFzZSBtYW51YWwgKGhlcmUgaXMgc2Ft OWczNSk6Cj4gaHR0cDovL3d3dy5hdG1lbC5jb20vSW1hZ2VzL2RvYzExMDUzLnBkZiBwYWdlIDEx ICjCpzQuMyBwYWNrYWdlIHBpbm91dCkKPiBpbiB0aGUgZmlsZSBhcmNoL2FybS9ib290L2R0cy9h dDkxc2FtOXg1LmR0c2kgeW91J3ZlIGdvdCB0aGUgdGhlCj4gYXRtZWwsbXV4LW1hc2sgbGlrZSB0 aGF0Ogo+Cj4gLyogcGVyaXBoQSAgcGVyaXBoQiAgICBwZXJpcGhDICAgICAqLwo+IDB4ZmZmZmZm ZmYgMHhmZmUwMzk5ZiAweGMwMDAwMDFjICAvKiBwaW9BICovCj4gMHgwMDA3ZmZmZiAweDgwMDBm ZTNmIDB4MDAwMDAwMDAgIC8qIHBpb0IgKi8KPiAweDgwMDAwMDAwIDB4MDdjMGZmZmYgMHhiODNm ZmZmZiAgLyogcGlvQyAqLwo+IDB4MDAzZmZmZmYgMHgwMDNmODAwMCAweDAwMDAwMDAwICAvKiBw aW9EICovCj4gCj4gTGV0J3MgdGFrZSB0aGUgUGlvQSAtIHBlcmlwaGVyYWwgQjogMHhmZmUwMzk5 Zgo+IEZyb20gdGhlIGRvY3VtZW50YXRpb24gdGFibGUgNC0zLCB3ZSBjYW4gZXh0cmFjdCB0aGUg Y29sdW1uIFBJTwo+IFBlcmlwZXJhbCBCIGZvciBhbGwgc2lnbmFscyBQQTAtUEEzMToKLi4uCj4g RWFjaCB0aW1lIGl0J3MgcG9zc2libGUgdG8gbXV4IGEgcGluIHRvIHRoZSBwZXJpcGhlcmFsIEIg ZnVuY3Rpb24gKGllCj4gd2hlbiB0aGVyZSdzIG5vICItLS0tLSIpIHRoZSBjb3JyZXNwb25kaW5n IGJpdCBpcyBzZXQ6Ci4uLgo+ID0+IHRoaXMgZ2l2ZXMgMHgzOTlmCgpBaCBPSy4gSXQgd291bGQg YmUgYSBnb29kIGlkZWEgdG8gYnJpZWZseSBkZXNjcmliZSB0aGlzIHByb2Nlc3MgaW4gdGhlCmJp bmRpbmcgZG9jdW1lbnQgSSB0aGluay4gSSBhc3N1bWUgdGhpcyBwcm9wZXJ0eSBleGlzdHMgdG8g YXZvaWQgdGhlCmtlcm5lbCBkcml2ZXIgaGF2aW5nIHRvIGNvbnRhaW4gdGFibGVzIGZvciBlYWNo IEF0bWVsIGRldmljZTsgdGhlIGRyaXZlcgppcyBnZW5lcmljLgpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkZXZpY2V0cmVlLWRpc2N1c3MgbWFpbGluZyBs aXN0CmRldmljZXRyZWUtZGlzY3Vzc0BsaXN0cy5vemxhYnMub3JnCmh0dHBzOi8vbGlzdHMub3ps YWJzLm9yZy9saXN0aW5mby9kZXZpY2V0cmVlLWRpc2N1c3MK