Re: [Qemu-devel] [PATCH v4 5/5] i8259: fix dynamically masking slave IRQs with IMR register

[Jan Kiszka <jan.kiszka@siemens.com>]

On 2012-09-03 13:11, Paolo Bonzini wrote:
> Il 03/09/2012 12:34, Jan Kiszka ha scritto:
>>>> Why is this a problem?  All of them use IRQ2 for a cascade, and initialize
>>>> icw3 to 0x4/0x2 (I checked OpenBIOS, rth's palcode for Alpha, and Linux).
>> IRQ2 is already hard-coded in QEMU (we had to patch this for our machine
>> emulation, but less in recent versions), that is not the point. I'm
>> concerned about the behavioral changes we are discussing here, ie. the
>> special handling of cascading interrupt inputs.
> 
> Yeah, it's quite interesting that the behavior isn't mentioned in the
> 8259 datasheets.  Still in retrospect it's hard to see how it can
> possibly work with edge-triggered cascaded inputs.

As I said: by avoiding the pattern Matthew generated in his test case.
That's not impossible. All the other OSes running fine against out PIC
models are proving this.

Jan

-- 
Siemens AG, Corporate Technology, CT RTC ITP SDP-DE
Corporate Competence Center Embedded Linux