Re: [PATCH V3 2/2] MIPS: make funcs preempt-safe for non-mipsr2 cpus

[David Daney <ddaney.cavm@gmail.com>]

On 09/03/2012 02:52 PM, Jim Quinlan wrote:
> For non MIPSr2 processors, such as the BMIPS 5000, calls to
> arch_local_irq_disable() and others may be preempted, and in doing
> so a stale value may be restored to c0_status.  This fix disables
> preemption for such processors prior to the call and enables it
> after the call.
>
> Those functions that needed this fix have been "outlined" to
> mips-atomic.c, as they are no longer good candidates for inlining.
>
> This bug was observed in a BMIPS 5000, occuring once every few hours
> in a continuous reboot test.  It was traced to the write_lock_irq()
> function which was being invoked in release_task() in exit.c.
> By placing a number of "nops" inbetween the mfc0/mtc0 pair in
> arch_local_irq_disable(), which is called by write_lock_irq(), we
> were able to greatly increase the occurance of this bug.  Similarly,
> the application of this commit silenced the bug.
>
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>

This one seems better too...

[...]
> diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
> new file mode 100644
> index 0000000..546eb25
> --- /dev/null
> +++ b/arch/mips/lib/mips-atomic.c
> @@ -0,0 +1,179 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
> + * Copyright (C) 1996 by Paul M. Antoine
> + * Copyright (C) 1999 Silicon Graphics
> + * Copyright (C) 2000 MIPS Technologies, Inc.
> + */
> +#include <asm/irqflags.h>
> +#include <asm/hazards.h>
> +#include <linux/compiler.h>
> +#include <linux/preempt.h>
> +
> +#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC)
> +
> +#if defined(CONFIG_PREEMPT)
> +#define arch_local_preempt_enable() preempt_enable()
> +#define arch_local_preempt_disable() preempt_disable()
> +#else
> +#define arch_local_preempt_enable()
> +#define arch_local_preempt_disable()
> +#endif
> +
> +
> +/*
> + * For cli() we have to insert nops to make sure that the new value
> + * has actually arrived in the status register before the end of this
> + * macro.
> + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
> + * no nops at all.
> + */
> +/*
> + * For TX49, operating only IE bit is not enough.
> + *
> + * If mfc0 $12 follows store and the mfc0 is last instruction of a
> + * page and fetching the next instruction causes TLB miss, the result
> + * of the mfc0 might wrongly contain EXL bit.
> + *
> + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
> + *
> + * Workaround: mask EXL bit of the result or place a nop before mfc0.
> + */
> +__asm__(
> +	"	.macro	arch_local_irq_disable\n"
> +	"	.set	push						\n"
> +	"	.set	noat						\n"
> +#ifdef CONFIG_MIPS_MT_SMTC
> +	"	mfc0	$1, $2, 1					\n"
> +	"	ori	$1, 0x400					\n"
> +	"	.set	noreorder					\n"
> +	"	mtc0	$1, $2, 1					\n"
> +#elif defined(CONFIG_CPU_MIPSR2)
> +	/* see irqflags.h for inline function */
> +#else
> +	"	mfc0	$1,$12						\n"
> +	"	ori	$1,0x1f						\n"
> +	"	xori	$1,0x1f						\n"
> +	"	.set	noreorder					\n"
> +	"	mtc0	$1,$12						\n"
> +#endif
> +	"	irq_disable_hazard					\n"
> +	"	.set	pop						\n"
> +	"	.endm							\n");
> +
> +void arch_local_irq_disable(void)
> +{
> +	arch_local_preempt_disable();
> +	__asm__ __volatile__(
> +		"arch_local_irq_disable"
> +		: /* no outputs */
> +		: /* no inputs */
> +		: "memory");
> +	arch_local_preempt_enable();
> +}

I think this function must be EXPORT_SYMBOL() too.

David Daney