From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TB0NA-0007wR-4R for qemu-devel@nongnu.org; Mon, 10 Sep 2012 05:33:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TB0N5-0002rL-07 for qemu-devel@nongnu.org; Mon, 10 Sep 2012 05:33:40 -0400 Received: from mout.web.de ([212.227.17.11]:57674) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TB0N4-0002rF-L5 for qemu-devel@nongnu.org; Mon, 10 Sep 2012 05:33:34 -0400 Message-ID: <504DB3E4.9010800@web.de> Date: Mon, 10 Sep 2012 11:33:24 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <1347240466-6152-1-git-send-email-mmogilvi_qemu@miniinfo.net> <1347240466-6152-6-git-send-email-mmogilvi_qemu@miniinfo.net> <504DAB38.4000407@redhat.com> <504DAE47.8090607@web.de> <504DB061.6060209@redhat.com> In-Reply-To: <504DB061.6060209@redhat.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig84753970C3277400C8D8E443" Subject: Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Paolo Bonzini , Matthew Ogilvie , "Maciej W. Rozycki" , qemu-devel@nongnu.org This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig84753970C3277400C8D8E443 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 2012-09-10 11:18, Avi Kivity wrote: > On 09/10/2012 12:09 PM, Jan Kiszka wrote: >> On 2012-09-10 10:56, Avi Kivity wrote: >>> On 09/10/2012 04:27 AM, Matthew Ogilvie wrote: >>>> Intel's definition of "edge triggered" means: "asserted with a >>>> low-to-high transition at the time an interrupt is registered and >>>> then kept high until the interrupt is served via one of the >>>> EOI mechanisms or goes away unhandled." >>>> >>>> So the only difference between edge triggered and level triggered >>>> is in the leading edge, with no difference in the trailing edge. >>> >>> Hard to believe. So an edge while cpu interrupts are disabled is ign= ored? >> >> No, this is about the PIC, not the CPU interrupt inputs. >=20 > I see, the interrupt is still sent to the processor; but IRR reflects > that status of the input line, not a "pending interrupt" status. >=20 > Will this survive live migration? If we clear IRR, then we must rely o= n > the other end to remember the IRQ, but if processor interrupts are > disabled there won't be an INTACK and the signal is lost. We clear the IRR as there is nothing to deliver to the CPU anymore. No IRQ source will drop its line as long as there is a reason for the IRQ, I checked the edge-using devices. So we can't lose anything. Jan --------------enig84753970C3277400C8D8E443 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.16 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://www.enigmail.net/ iEYEARECAAYFAlBNs+QACgkQitSsb3rl5xTPIQCglQ4jxaTeuvoSYH2J3Sso0MhN qs8AoMn5tnr00UhPzoU642fUJgii07D2 =dvhc -----END PGP SIGNATURE----- --------------enig84753970C3277400C8D8E443--