Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C

[Don Slutz <Don@CloudSwitch.Com>]

On 09/10/12 09:04, Igor Mammedov wrote:
> On Mon, 10 Sep 2012 14:31:49 +0200
> Igor Mammedov <imammedo@redhat.com> wrote:
>
>> On Mon, 10 Sep 2012 14:18:38 +0200
>> Igor Mammedov <imammedo@redhat.com> wrote:
>>
>>> On Wed,  5 Sep 2012 17:41:10 -0300
>>> Eduardo Habkost <ehabkost@redhat.com> wrote:
>>>
>>>> Those models are maintained by QEMU and may require compatibility code
>>>> to be added when making some changes. Keeping the data in the C source
>>>> code should make it simpler to handle those details.
>>>>
>>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>>>> ---
>>>>   sysconfigs/target/cpus-x86_64.conf | 129 +---------------------
>>>>   target-i386/cpu.c                  | 219
>>>> +++++++++++++++++++++++++++++++++++++ 2 files changed, 220
>>>> insertions(+), 128 deletions(-)
>>>>
>>>> diff --git a/sysconfigs/target/cpus-x86_64.conf
>>>> b/sysconfigs/target/cpus-x86_64.conf index cee0ea9..3902189 100644
>>>> --- a/sysconfigs/target/cpus-x86_64.conf
>>>> +++ b/sysconfigs/target/cpus-x86_64.conf
>>>> @@ -1,128 +1 @@
>>>> -# x86 CPU MODELS
>>>> -
>>>> -[cpudef]
>>>> -   name = "Conroe"
>>>> -   level = "2"
>>>> -   vendor = "GenuineIntel"
>>>> -   family = "6"
>>>> -   model = "2"
>>>> -   stepping = "3"
>>>> -   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr
>>>> sep apic cx8 mce pae msr tsc pse de fpu"
>>>> -   feature_ecx = "ssse3 sse3"
>>>> -   extfeature_edx = "i64 xd syscall"
>>> ...
>>>> +        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
>>>> CPUID_EXT2_SYSCALL,
>>> Silent fix, replacing i64 with CPUID_EXT2_LM
>>> looks like "i64" is mistake and never worked. In Intel & AMD cpuid guides
>> Actually it works when setting feature fields because it uses
>> setfeatures(), however setting i64 will set wrong bit if it's set using
>> add_flagname_to_bitmaps()
> I'm wrong, and sorry for noise. I mixed up ia64 from feature_name with i64
> from ext2_feature_name.
>
> But question unrelated to this patch is still stand if ia64 is valid bit for
> 01.EDX[30]?
>
>
Intel® Processor Identification
and the CPUID Instruction
Application Note 485
January 2006

Order Number: 241618-030

...

Updated Table 3-5 to include the feature flag definition (EDX[30]) for 
IA64 capabilities.
...
30 IA64 IA64 Capabilities The processor is a member of the Intel® 
Itanium® processor family
                            and currently operating in IA32 emulation mode.

---------------

Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and 
http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64)



But the newest version I found (241618-037, January 2011) is back to 
Reserved.


    -Don Slutz