From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TB5gO-0000a6-15 for qemu-devel@nongnu.org; Mon, 10 Sep 2012 11:13:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TB5gE-0003Kq-Ow for qemu-devel@nongnu.org; Mon, 10 Sep 2012 11:13:51 -0400 Received: from cantor2.suse.de ([195.135.220.15]:48703 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TB5gE-0003Km-F2 for qemu-devel@nongnu.org; Mon, 10 Sep 2012 11:13:42 -0400 Message-ID: <504E03A3.7020307@suse.de> Date: Mon, 10 Sep 2012 17:13:39 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1346877673-9136-1-git-send-email-ehabkost@redhat.com> <1346877673-9136-5-git-send-email-ehabkost@redhat.com> <20120910141838.19636d67@nial.usersys.redhat.com> <20120910143149.500ba268@nial.usersys.redhat.com> <20120910150430.7a425e92@nial.usersys.redhat.com> <504DFE4E.4030106@CloudSwitch.Com> <504E001F.80509@suse.de> <20120910150750.GH2886@otherpad.lan.raisama.net> In-Reply-To: <20120910150750.GH2886@otherpad.lan.raisama.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/7] move CPU models from cpus-x86_64.conf to C List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost Cc: Igor Mammedov , Don Slutz , qemu-devel@nongnu.org, Anthony Liguori , Peter Maydell Am 10.09.2012 17:07, schrieb Eduardo Habkost: > On Mon, Sep 10, 2012 at 04:58:39PM +0200, Andreas F=E4rber wrote: >> Am 10.09.2012 16:50, schrieb Don Slutz: >>> On 09/10/12 09:04, Igor Mammedov wrote: >>>> But question unrelated to this patch is still stand if ia64 is valid >>>> bit for >>>> 01.EDX[30]? >>>> >>>> >>> Intel=AE Processor Identification >>> and the CPUID Instruction >>> Application Note 485 >>> January 2006 >>> >>> Order Number: 241618-030 >>> >>> ... >>> >>> Updated Table 3-5 to include the feature flag definition (EDX[30]) fo= r >>> IA64 capabilities. >>> ... >>> 30 IA64 IA64 Capabilities The processor is a member of the Intel=AE >>> Itanium=AE processor family >>> and currently operating in IA32 emulation = mode. >>> >>> --------------- >>> >>> Says that it is. Along with http://en.wikipedia.org/wiki/CPUID and >>> http://www.sandpile.org/x86/cpuid.htm#level_0000_0001h (IA-64) >> >> Don't those semantics contradict the use in qemu-system-x86_64 or >> qemu-system-i386 rather than qemu-system-ia64 then? We don't model ia6= 4 >> CPUs here (just like we don't model ppc64 CPUs in ppc) so the flag cou= ld >> never become 1 IIUC. >=20 > Correct, and the bit is always filtered out on both TCG and KVM modes. > The name is in the table because we know the name/meaning of that > feature bit, but it's impossible to enable it. >=20 > That said, I don't mind removing it from the table just to avoid > confusion, but I also wouldn't mind keeping it (as it's harmless). No objections from my side against having it for informational purpose. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg