From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE4yB-0006tH-MG for qemu-devel@nongnu.org; Tue, 18 Sep 2012 17:04:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TE4yA-0001Wp-FL for qemu-devel@nongnu.org; Tue, 18 Sep 2012 17:04:35 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34994 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE4yA-0001Wd-8N for qemu-devel@nongnu.org; Tue, 18 Sep 2012 17:04:34 -0400 Message-ID: <5058E1DE.4030402@suse.de> Date: Tue, 18 Sep 2012 23:04:30 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1347224784-19472-1-git-send-email-rth@twiddle.net> <1347224784-19472-87-git-send-email-rth@twiddle.net> <504FA888.70808@twiddle.net> In-Reply-To: <504FA888.70808@twiddle.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 086/126] target-s390: Convert CLST, MVST List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Blue Swirl , qemu-devel@nongnu.org On 09/11/2012 11:09 PM, Richard Henderson wrote: > On 09/11/2012 12:11 PM, Blue Swirl wrote: >> PSW_MASK_64 bit could be added to TB flags and that could be checked >> during translation, then the mask needs to be applied only when the >> mode is active. Whether that actually improves performance depends on >> how often the bit is changed. Also all PSW writes need to be handled, >> possibly causing a TB flush. > Actually I'm not sure why we check this at all, given that we only > actually handle 64-bit mode -- at least as documented by the code > implementing the SET ADDRESS MODE instruction. For kernel code, we only support 64 bit mode, yes. But for user space code, we need to support 31-bit mode to enable Debian to work. They still run all user space in 31-bit mode. > That said, we do encode the bit in TB flags, and we do perform this > masking for qemu loads performed within the TB. No TB flushes are > required because we simply don't match TBs with different flags. > > As for clst, mvst, srst, I thought about performing the masking in > the TB, but didn't figure it was worth it. Do you have an opinion, Alex? I don't know if it's worth it either. When calling anything with address parameters we already need to save off all registers to env, since we could take a page fault any time. So moving code into TCG context shouldn't improve anything performance wise. Alex