diff for duplicates of <50601470190398@web16g.yandex.ru> diff --git a/a/1.txt b/N1/1.txt index 583d512..207ac3d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,104 +4,104 @@ > Hi Icenowy, > > On 08/02/2016 12:13 AM, Icenowy Zheng wrote: ->> A64 SoC features a MMC controller which need only the mod clock, and can ->> calibrate delay by itself. This patch adds support for the new MMC ->> controller IP core. +>> ?A64 SoC features a MMC controller which need only the mod clock, and can +>> ?calibrate delay by itself. This patch adds support for the new MMC +>> ?controller IP core. >> ->> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> ->> --- ->> Changes in v2: ->> - Rebased on Hans de Goede's patchset. ->> Changes in v3: ->> - Tidy up based on Hans de Goede's opinions. +>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +>> ?--- +>> ?Changes in v2: +>> ?- Rebased on Hans de Goede's patchset. +>> ?Changes in v3: +>> ?- Tidy up based on Hans de Goede's opinions. >> ->> drivers/mmc/host/sunxi-mmc.c | 66 ++++++++++++++++++++++++++++++++++++++++++++ ->> 1 file changed, 66 insertions(+) +>> ??drivers/mmc/host/sunxi-mmc.c | 66 ++++++++++++++++++++++++++++++++++++++++++++ +>> ??1 file changed, 66 insertions(+) >> ->> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c ->> index 2ec91ce..3c26180 100644 ->> --- a/drivers/mmc/host/sunxi-mmc.c ->> +++ b/drivers/mmc/host/sunxi-mmc.c ->> @@ -72,6 +72,13 @@ ->> #define SDXC_REG_CHDA (0x90) ->> #define SDXC_REG_CBDA (0x94) +>> ?diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c +>> ?index 2ec91ce..3c26180 100644 +>> ?--- a/drivers/mmc/host/sunxi-mmc.c +>> ?+++ b/drivers/mmc/host/sunxi-mmc.c +>> ?@@ -72,6 +72,13 @@ +>> ??#define SDXC_REG_CHDA (0x90) +>> ??#define SDXC_REG_CBDA (0x94) >> ->> +/* New registers introduced in A64 */ ->> +#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ ->> +#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ ->> +#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ ->> +#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ ->> +#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ ->> + ->> #define mmc_readl(host, reg) \ ->> readl((host)->reg_base + SDXC_##reg) ->> #define mmc_writel(host, reg, value) \ ->> @@ -217,6 +224,15 @@ ->> #define SDXC_CLK_50M_DDR 3 ->> #define SDXC_CLK_50M_DDR_8BIT 4 +>> ?+/* New registers introduced in A64 */ +>> ?+#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ +>> ?+#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ +>> ?+#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ +>> ?+#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ +>> ?+#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ +>> ?+ +>> ??#define mmc_readl(host, reg) \ +>> ??????????readl((host)->reg_base + SDXC_##reg) +>> ??#define mmc_writel(host, reg, value) \ +>> ?@@ -217,6 +224,15 @@ +>> ??#define SDXC_CLK_50M_DDR 3 +>> ??#define SDXC_CLK_50M_DDR_8BIT 4 >> ->> +#define SDXC_2X_TIMING_MODE BIT(31) ->> + ->> +#define SDXC_CAL_START BIT(15) ->> +#define SDXC_CAL_DONE BIT(14) ->> +#define SDXC_CAL_DL_SHIFT 8 ->> +#define SDXC_CAL_DL_SW_EN BIT(7) ->> +#define SDXC_CAL_DL_SW_SHIFT 0 ->> +#define SDXC_CAL_DL_MASK 0x3f ->> + ->> struct sunxi_mmc_clk_delay { ->> u32 output; ->> u32 sample; ->> @@ -232,6 +248,9 @@ struct sunxi_idma_des { ->> struct sunxi_mmc_cfg { ->> u32 idma_des_size_bits; ->> const struct sunxi_mmc_clk_delay *clk_delays; ->> + ->> + /* does the IP block support autocalibration? */ ->> + bool can_calibrate; ->> }; +>> ?+#define SDXC_2X_TIMING_MODE BIT(31) +>> ?+ +>> ?+#define SDXC_CAL_START BIT(15) +>> ?+#define SDXC_CAL_DONE BIT(14) +>> ?+#define SDXC_CAL_DL_SHIFT 8 +>> ?+#define SDXC_CAL_DL_SW_EN BIT(7) +>> ?+#define SDXC_CAL_DL_SW_SHIFT 0 +>> ?+#define SDXC_CAL_DL_MASK 0x3f +>> ?+ +>> ??struct sunxi_mmc_clk_delay { +>> ??????????u32 output; +>> ??????????u32 sample; +>> ?@@ -232,6 +248,9 @@ struct sunxi_idma_des { +>> ??struct sunxi_mmc_cfg { +>> ??????????u32 idma_des_size_bits; +>> ??????????const struct sunxi_mmc_clk_delay *clk_delays; +>> ?+ +>> ?+ /* does the IP block support autocalibration? */ +>> ?+ bool can_calibrate; +>> ??}; >> ->> struct sunxi_mmc_host { ->> @@ -657,6 +676,38 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) ->> return 0; ->> } +>> ??struct sunxi_mmc_host { +>> ?@@ -657,6 +676,38 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) +>> ??????????return 0; +>> ??} >> ->> +static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, ->> + struct mmc_ios *ios, int reg_off) +>> ?+static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, +>> ?+ struct mmc_ios *ios, int reg_off) > > Where is mmc_ios structure used in this function? > And why passing the reg_off? > ->> +{ ->> + u32 reg = readl(host->reg_base + reg_off); ->> + u32 delay; +>> ?+{ +>> ?+ u32 reg = readl(host->reg_base + reg_off); +>> ?+ u32 delay; > > delay doesn't need to use u32.. > reg_off is only passed with SDXC_REG_SAMP_DL_REG..this function doesn't reuse anywhere. A64 have another register which has the same calibration program. However, it's only present on the third MMC controller, which is usually used with eMMC. Currently, no device with eMMC and A64 is easy to hack. (The model device is A64, which have not used MMC2) > ->> + ->> + if (!host->cfg->can_calibrate) ->> + return 0; ->> + ->> + reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT); ->> + reg &= ~SDXC_CAL_DL_SW_EN; ->> + ->> + writel(reg | SDXC_CAL_START, host->reg_base + reg_off); ->> + ->> + dev_dbg(mmc_dev(host->mmc), "calibration started\n"); ->> + ->> + while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE)) ->> + cpu_relax(); +>> ?+ +>> ?+ if (!host->cfg->can_calibrate) +>> ?+ return 0; +>> ?+ +>> ?+ reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT); +>> ?+ reg &= ~SDXC_CAL_DL_SW_EN; +>> ?+ +>> ?+ writel(reg | SDXC_CAL_START, host->reg_base + reg_off); +>> ?+ +>> ?+ dev_dbg(mmc_dev(host->mmc), "calibration started\n"); +>> ?+ +>> ?+ while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE)) +>> ?+ cpu_relax(); > > If never hit this condition, infinite loop? I will soon add a timeout for it. > ->> + ->> + delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK; ->> + ->> + reg &= ~SDXC_CAL_START; ->> + reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN; +>> ?+ +>> ?+ delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK; +>> ?+ +>> ?+ reg &= ~SDXC_CAL_START; +>> ?+ reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN; > > Something is strange. It seems to maintain the delay value. It acquired the delay value from part of the register, and then set it in another. @@ -111,29 +111,29 @@ It acquired the delay value from part of the register, and then set it in anothe > > is it same thing? > ->> + ->> + writel(reg, host->reg_base + reg_off); ->> + ->> + dev_dbg(mmc_dev(host->mmc), "calibration ended, res is 0x%x\n", reg); +>> ?+ +>> ?+ writel(reg, host->reg_base + reg_off); +>> ?+ +>> ?+ dev_dbg(mmc_dev(host->mmc), "calibration ended, res is 0x%x\n", reg); > > s/res is/reg is ? maybe it's right. > ->> + ->> + /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */ ->> + return 0; ->> +} ->> + ->> static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, ->> struct mmc_ios *ios, u32 rate) ->> { ->> @@ -731,6 +782,10 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, ->> if (ret) ->> return ret; +>> ?+ +>> ?+ /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */ +>> ?+ return 0; +>> ?+} +>> ?+ +>> ??static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, +>> ?????????????????????????????????????struct mmc_ios *ios, u32 rate) +>> ??{ +>> ?@@ -731,6 +782,10 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, +>> ??????????if (ret) +>> ??????????????????return ret; >> ->> + ret = sunxi_mmc_calibrate(host, ios, SDXC_REG_SAMP_DL_REG); ->> + if (ret) ->> + return ret; +>> ?+ ret = sunxi_mmc_calibrate(host, ios, SDXC_REG_SAMP_DL_REG); +>> ?+ if (ret) +>> ?+ return ret; > > Never enter this condition. sunxi_mmc_calibrate() is always returned 0. A timeout is TODO... @@ -141,52 +141,47 @@ A timeout is TODO... > Best Regards, > Jaehoon Chung > ->> + ->> return sunxi_mmc_oclk_onoff(host, 1); ->> } +>> ?+ +>> ??????????return sunxi_mmc_oclk_onoff(host, 1); +>> ??} >> ->> @@ -982,21 +1037,31 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { ->> static const struct sunxi_mmc_cfg sun4i_a10_cfg = { ->> .idma_des_size_bits = 13, ->> .clk_delays = NULL, ->> + .can_calibrate = false, ->> }; +>> ?@@ -982,21 +1037,31 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { +>> ??static const struct sunxi_mmc_cfg sun4i_a10_cfg = { +>> ??????????.idma_des_size_bits = 13, +>> ??????????.clk_delays = NULL, +>> ?+ .can_calibrate = false, +>> ??}; >> ->> static const struct sunxi_mmc_cfg sun5i_a13_cfg = { ->> .idma_des_size_bits = 16, ->> .clk_delays = NULL, ->> + .can_calibrate = false, ->> }; +>> ??static const struct sunxi_mmc_cfg sun5i_a13_cfg = { +>> ??????????.idma_des_size_bits = 16, +>> ??????????.clk_delays = NULL, +>> ?+ .can_calibrate = false, +>> ??}; >> ->> static const struct sunxi_mmc_cfg sun7i_a20_cfg = { ->> .idma_des_size_bits = 16, ->> .clk_delays = sunxi_mmc_clk_delays, ->> + .can_calibrate = false, ->> }; +>> ??static const struct sunxi_mmc_cfg sun7i_a20_cfg = { +>> ??????????.idma_des_size_bits = 16, +>> ??????????.clk_delays = sunxi_mmc_clk_delays, +>> ?+ .can_calibrate = false, +>> ??}; >> ->> static const struct sunxi_mmc_cfg sun9i_a80_cfg = { ->> .idma_des_size_bits = 16, ->> .clk_delays = sun9i_mmc_clk_delays, ->> + .can_calibrate = false, ->> +}; ->> + ->> +static const struct sunxi_mmc_cfg sun50i_a64_cfg = { ->> + .idma_des_size_bits = 16, ->> + .clk_delays = NULL, ->> + .can_calibrate = true, ->> }; +>> ??static const struct sunxi_mmc_cfg sun9i_a80_cfg = { +>> ??????????.idma_des_size_bits = 16, +>> ??????????.clk_delays = sun9i_mmc_clk_delays, +>> ?+ .can_calibrate = false, +>> ?+}; +>> ?+ +>> ?+static const struct sunxi_mmc_cfg sun50i_a64_cfg = { +>> ?+ .idma_des_size_bits = 16, +>> ?+ .clk_delays = NULL, +>> ?+ .can_calibrate = true, +>> ??}; >> ->> static const struct of_device_id sunxi_mmc_of_match[] = { ->> @@ -1004,6 +1069,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = { ->> { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, ->> { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, ->> { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, ->> + { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, ->> { /* sentinel */ } ->> }; ->> MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); - -_______________________________________________ -linux-arm-kernel mailing list -linux-arm-kernel@lists.infradead.org -http://lists.infradead.org/mailman/listinfo/linux-arm-kernel +>> ??static const struct of_device_id sunxi_mmc_of_match[] = { +>> ?@@ -1004,6 +1069,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = { +>> ??????????{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, +>> ??????????{ .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, +>> ??????????{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, +>> ?+ { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, +>> ??????????{ /* sentinel */ } +>> ??}; +>> ??MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); diff --git a/a/content_digest b/N1/content_digest index b508bc6..8da8cbb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,21 +2,10 @@ "ref\0CGME20160801151434epcas1p15f57862a238cf493445ed667f37a8a88@epcas1p1.samsung.com\0" "ref\020160801151351.51854-3-icenowy@aosc.xyz\0" "ref\057A13028.2030506@samsung.com\0" - "From\0Icenowy Zheng <icenowy@aosc.xyz>\0" - "Subject\0Re: [PATCH v3 2/2] mmc: host: sunxi: add support for A64 mmc controller\0" + "From\0icenowy@aosc.xyz (Icenowy Zheng)\0" + "Subject\0[PATCH v3 2/2] mmc: host: sunxi: add support for A64 mmc controller\0" "Date\0Wed, 03 Aug 2016 10:13:18 +0800\0" - "To\0Jaehoon Chung <jh80.chung@samsung.com>" - Rob Herring <robh+dt@kernel.org> - Maxime Ripard <maxime.ripard@free-electrons.com> - Chen-Yu Tsai <wens@csie.org> - Ulf Hansson <ulf.hansson@linaro.org> - " Hans de Goede <hdegoede@redhat.com>\0" - "Cc\0Mark Rutland <mark.rutland@arm.com>" - devicetree@vger.kernel.org <devicetree@vger.kernel.org> - Michal Suchanek <hramrach@gmail.com> - linux-mmc@vger.kernel.org <linux-mmc@vger.kernel.org> - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" @@ -25,104 +14,104 @@ "> Hi Icenowy,\n" ">\n" "> On 08/02/2016 12:13 AM, Icenowy Zheng wrote:\n" - ">> \302\240A64 SoC features a MMC controller which need only the mod clock, and can\n" - ">> \302\240calibrate delay by itself. This patch adds support for the new MMC\n" - ">> \302\240controller IP core.\n" + ">> ?A64 SoC features a MMC controller which need only the mod clock, and can\n" + ">> ?calibrate delay by itself. This patch adds support for the new MMC\n" + ">> ?controller IP core.\n" ">>\n" - ">> \302\240Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>\n" - ">> \302\240---\n" - ">> \302\240Changes in v2:\n" - ">> \302\240- Rebased on Hans de Goede's patchset.\n" - ">> \302\240Changes in v3:\n" - ">> \302\240- Tidy up based on Hans de Goede's opinions.\n" + ">> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>\n" + ">> ?---\n" + ">> ?Changes in v2:\n" + ">> ?- Rebased on Hans de Goede's patchset.\n" + ">> ?Changes in v3:\n" + ">> ?- Tidy up based on Hans de Goede's opinions.\n" ">>\n" - ">> \302\240\302\240drivers/mmc/host/sunxi-mmc.c | 66 ++++++++++++++++++++++++++++++++++++++++++++\n" - ">> \302\240\302\2401 file changed, 66 insertions(+)\n" + ">> ??drivers/mmc/host/sunxi-mmc.c | 66 ++++++++++++++++++++++++++++++++++++++++++++\n" + ">> ??1 file changed, 66 insertions(+)\n" ">>\n" - ">> \302\240diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c\n" - ">> \302\240index 2ec91ce..3c26180 100644\n" - ">> \302\240--- a/drivers/mmc/host/sunxi-mmc.c\n" - ">> \302\240+++ b/drivers/mmc/host/sunxi-mmc.c\n" - ">> \302\240@@ -72,6 +72,13 @@\n" - ">> \302\240\302\240#define SDXC_REG_CHDA (0x90)\n" - ">> \302\240\302\240#define SDXC_REG_CBDA (0x94)\n" + ">> ?diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c\n" + ">> ?index 2ec91ce..3c26180 100644\n" + ">> ?--- a/drivers/mmc/host/sunxi-mmc.c\n" + ">> ?+++ b/drivers/mmc/host/sunxi-mmc.c\n" + ">> ?@@ -72,6 +72,13 @@\n" + ">> ??#define SDXC_REG_CHDA (0x90)\n" + ">> ??#define SDXC_REG_CBDA (0x94)\n" ">>\n" - ">> \302\240+/* New registers introduced in A64 */\n" - ">> \302\240+#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */\n" - ">> \302\240+#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */\n" - ">> \302\240+#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */\n" - ">> \302\240+#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */\n" - ">> \302\240+#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */\n" - ">> \302\240+\n" - ">> \302\240\302\240#define mmc_readl(host, reg) \\\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240readl((host)->reg_base + SDXC_##reg)\n" - ">> \302\240\302\240#define mmc_writel(host, reg, value) \\\n" - ">> \302\240@@ -217,6 +224,15 @@\n" - ">> \302\240\302\240#define SDXC_CLK_50M_DDR 3\n" - ">> \302\240\302\240#define SDXC_CLK_50M_DDR_8BIT 4\n" + ">> ?+/* New registers introduced in A64 */\n" + ">> ?+#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */\n" + ">> ?+#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */\n" + ">> ?+#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */\n" + ">> ?+#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */\n" + ">> ?+#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */\n" + ">> ?+\n" + ">> ??#define mmc_readl(host, reg) \\\n" + ">> ??????????readl((host)->reg_base + SDXC_##reg)\n" + ">> ??#define mmc_writel(host, reg, value) \\\n" + ">> ?@@ -217,6 +224,15 @@\n" + ">> ??#define SDXC_CLK_50M_DDR 3\n" + ">> ??#define SDXC_CLK_50M_DDR_8BIT 4\n" ">>\n" - ">> \302\240+#define SDXC_2X_TIMING_MODE BIT(31)\n" - ">> \302\240+\n" - ">> \302\240+#define SDXC_CAL_START BIT(15)\n" - ">> \302\240+#define SDXC_CAL_DONE BIT(14)\n" - ">> \302\240+#define SDXC_CAL_DL_SHIFT 8\n" - ">> \302\240+#define SDXC_CAL_DL_SW_EN BIT(7)\n" - ">> \302\240+#define SDXC_CAL_DL_SW_SHIFT 0\n" - ">> \302\240+#define SDXC_CAL_DL_MASK 0x3f\n" - ">> \302\240+\n" - ">> \302\240\302\240struct sunxi_mmc_clk_delay {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 output;\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 sample;\n" - ">> \302\240@@ -232,6 +248,9 @@ struct sunxi_idma_des {\n" - ">> \302\240\302\240struct sunxi_mmc_cfg {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 idma_des_size_bits;\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240const struct sunxi_mmc_clk_delay *clk_delays;\n" - ">> \302\240+\n" - ">> \302\240+ /* does the IP block support autocalibration? */\n" - ">> \302\240+ bool can_calibrate;\n" - ">> \302\240\302\240};\n" + ">> ?+#define SDXC_2X_TIMING_MODE BIT(31)\n" + ">> ?+\n" + ">> ?+#define SDXC_CAL_START BIT(15)\n" + ">> ?+#define SDXC_CAL_DONE BIT(14)\n" + ">> ?+#define SDXC_CAL_DL_SHIFT 8\n" + ">> ?+#define SDXC_CAL_DL_SW_EN BIT(7)\n" + ">> ?+#define SDXC_CAL_DL_SW_SHIFT 0\n" + ">> ?+#define SDXC_CAL_DL_MASK 0x3f\n" + ">> ?+\n" + ">> ??struct sunxi_mmc_clk_delay {\n" + ">> ??????????u32 output;\n" + ">> ??????????u32 sample;\n" + ">> ?@@ -232,6 +248,9 @@ struct sunxi_idma_des {\n" + ">> ??struct sunxi_mmc_cfg {\n" + ">> ??????????u32 idma_des_size_bits;\n" + ">> ??????????const struct sunxi_mmc_clk_delay *clk_delays;\n" + ">> ?+\n" + ">> ?+ /* does the IP block support autocalibration? */\n" + ">> ?+ bool can_calibrate;\n" + ">> ??};\n" ">>\n" - ">> \302\240\302\240struct sunxi_mmc_host {\n" - ">> \302\240@@ -657,6 +676,38 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" - ">> \302\240\302\240}\n" + ">> ??struct sunxi_mmc_host {\n" + ">> ?@@ -657,6 +676,38 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)\n" + ">> ??????????return 0;\n" + ">> ??}\n" ">>\n" - ">> \302\240+static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host,\n" - ">> \302\240+ struct mmc_ios *ios, int reg_off)\n" + ">> ?+static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host,\n" + ">> ?+ struct mmc_ios *ios, int reg_off)\n" ">\n" "> Where is mmc_ios structure used in this function?\n" "> And why passing the reg_off?\n" ">\n" - ">> \302\240+{\n" - ">> \302\240+ u32 reg = readl(host->reg_base + reg_off);\n" - ">> \302\240+ u32 delay;\n" + ">> ?+{\n" + ">> ?+ u32 reg = readl(host->reg_base + reg_off);\n" + ">> ?+ u32 delay;\n" ">\n" "> delay doesn't need to use u32..\n" "> reg_off is only passed with SDXC_REG_SAMP_DL_REG..this function doesn't reuse anywhere.\n" "A64 have another register which has the same calibration program. However, it's only present on the third MMC controller, which is usually used with eMMC. Currently, no device with eMMC and A64 is easy to hack. (The model device is A64, which have not used MMC2)\n" ">\n" - ">> \302\240+\n" - ">> \302\240+ if (!host->cfg->can_calibrate)\n" - ">> \302\240+ return 0;\n" - ">> \302\240+\n" - ">> \302\240+ reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT);\n" - ">> \302\240+ reg &= ~SDXC_CAL_DL_SW_EN;\n" - ">> \302\240+\n" - ">> \302\240+ writel(reg | SDXC_CAL_START, host->reg_base + reg_off);\n" - ">> \302\240+\n" - ">> \302\240+ dev_dbg(mmc_dev(host->mmc), \"calibration started\\n\");\n" - ">> \302\240+\n" - ">> \302\240+ while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE))\n" - ">> \302\240+ cpu_relax();\n" + ">> ?+\n" + ">> ?+ if (!host->cfg->can_calibrate)\n" + ">> ?+ return 0;\n" + ">> ?+\n" + ">> ?+ reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT);\n" + ">> ?+ reg &= ~SDXC_CAL_DL_SW_EN;\n" + ">> ?+\n" + ">> ?+ writel(reg | SDXC_CAL_START, host->reg_base + reg_off);\n" + ">> ?+\n" + ">> ?+ dev_dbg(mmc_dev(host->mmc), \"calibration started\\n\");\n" + ">> ?+\n" + ">> ?+ while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE))\n" + ">> ?+ cpu_relax();\n" ">\n" "> If never hit this condition, infinite loop?\n" "I will soon add a timeout for it.\n" ">\n" - ">> \302\240+\n" - ">> \302\240+ delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK;\n" - ">> \302\240+\n" - ">> \302\240+ reg &= ~SDXC_CAL_START;\n" - ">> \302\240+ reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN;\n" + ">> ?+\n" + ">> ?+ delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK;\n" + ">> ?+\n" + ">> ?+ reg &= ~SDXC_CAL_START;\n" + ">> ?+ reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN;\n" ">\n" "> Something is strange. It seems to maintain the delay value.\n" "It acquired the delay value from part of the register, and then set it in another.\n" @@ -132,29 +121,29 @@ ">\n" "> is it same thing?\n" ">\n" - ">> \302\240+\n" - ">> \302\240+ writel(reg, host->reg_base + reg_off);\n" - ">> \302\240+\n" - ">> \302\240+ dev_dbg(mmc_dev(host->mmc), \"calibration ended, res is 0x%x\\n\", reg);\n" + ">> ?+\n" + ">> ?+ writel(reg, host->reg_base + reg_off);\n" + ">> ?+\n" + ">> ?+ dev_dbg(mmc_dev(host->mmc), \"calibration ended, res is 0x%x\\n\", reg);\n" ">\n" "> s/res is/reg is ?\n" "maybe it's right.\n" ">\n" - ">> \302\240+\n" - ">> \302\240+ /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */\n" - ">> \302\240+ return 0;\n" - ">> \302\240+}\n" - ">> \302\240+\n" - ">> \302\240\302\240static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct mmc_ios *ios, u32 rate)\n" - ">> \302\240\302\240{\n" - ">> \302\240@@ -731,6 +782,10 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" + ">> ?+\n" + ">> ?+ /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */\n" + ">> ?+ return 0;\n" + ">> ?+}\n" + ">> ?+\n" + ">> ??static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,\n" + ">> ?????????????????????????????????????struct mmc_ios *ios, u32 rate)\n" + ">> ??{\n" + ">> ?@@ -731,6 +782,10 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,\n" + ">> ??????????if (ret)\n" + ">> ??????????????????return ret;\n" ">>\n" - ">> \302\240+ ret = sunxi_mmc_calibrate(host, ios, SDXC_REG_SAMP_DL_REG);\n" - ">> \302\240+ if (ret)\n" - ">> \302\240+ return ret;\n" + ">> ?+ ret = sunxi_mmc_calibrate(host, ios, SDXC_REG_SAMP_DL_REG);\n" + ">> ?+ if (ret)\n" + ">> ?+ return ret;\n" ">\n" "> Never enter this condition. sunxi_mmc_calibrate() is always returned 0.\n" "A timeout is TODO...\n" @@ -162,54 +151,49 @@ "> Best Regards,\n" "> Jaehoon Chung\n" ">\n" - ">> \302\240+\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return sunxi_mmc_oclk_onoff(host, 1);\n" - ">> \302\240\302\240}\n" + ">> ?+\n" + ">> ??????????return sunxi_mmc_oclk_onoff(host, 1);\n" + ">> ??}\n" ">>\n" - ">> \302\240@@ -982,21 +1037,31 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {\n" - ">> \302\240\302\240static const struct sunxi_mmc_cfg sun4i_a10_cfg = {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.idma_des_size_bits = 13,\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.clk_delays = NULL,\n" - ">> \302\240+ .can_calibrate = false,\n" - ">> \302\240\302\240};\n" + ">> ?@@ -982,21 +1037,31 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {\n" + ">> ??static const struct sunxi_mmc_cfg sun4i_a10_cfg = {\n" + ">> ??????????.idma_des_size_bits = 13,\n" + ">> ??????????.clk_delays = NULL,\n" + ">> ?+ .can_calibrate = false,\n" + ">> ??};\n" ">>\n" - ">> \302\240\302\240static const struct sunxi_mmc_cfg sun5i_a13_cfg = {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.idma_des_size_bits = 16,\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.clk_delays = NULL,\n" - ">> \302\240+ .can_calibrate = false,\n" - ">> \302\240\302\240};\n" + ">> ??static const struct sunxi_mmc_cfg sun5i_a13_cfg = {\n" + ">> ??????????.idma_des_size_bits = 16,\n" + ">> ??????????.clk_delays = NULL,\n" + ">> ?+ .can_calibrate = false,\n" + ">> ??};\n" ">>\n" - ">> \302\240\302\240static const struct sunxi_mmc_cfg sun7i_a20_cfg = {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.idma_des_size_bits = 16,\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.clk_delays = sunxi_mmc_clk_delays,\n" - ">> \302\240+ .can_calibrate = false,\n" - ">> \302\240\302\240};\n" + ">> ??static const struct sunxi_mmc_cfg sun7i_a20_cfg = {\n" + ">> ??????????.idma_des_size_bits = 16,\n" + ">> ??????????.clk_delays = sunxi_mmc_clk_delays,\n" + ">> ?+ .can_calibrate = false,\n" + ">> ??};\n" ">>\n" - ">> \302\240\302\240static const struct sunxi_mmc_cfg sun9i_a80_cfg = {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.idma_des_size_bits = 16,\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.clk_delays = sun9i_mmc_clk_delays,\n" - ">> \302\240+ .can_calibrate = false,\n" - ">> \302\240+};\n" - ">> \302\240+\n" - ">> \302\240+static const struct sunxi_mmc_cfg sun50i_a64_cfg = {\n" - ">> \302\240+ .idma_des_size_bits = 16,\n" - ">> \302\240+ .clk_delays = NULL,\n" - ">> \302\240+ .can_calibrate = true,\n" - ">> \302\240\302\240};\n" + ">> ??static const struct sunxi_mmc_cfg sun9i_a80_cfg = {\n" + ">> ??????????.idma_des_size_bits = 16,\n" + ">> ??????????.clk_delays = sun9i_mmc_clk_delays,\n" + ">> ?+ .can_calibrate = false,\n" + ">> ?+};\n" + ">> ?+\n" + ">> ?+static const struct sunxi_mmc_cfg sun50i_a64_cfg = {\n" + ">> ?+ .idma_des_size_bits = 16,\n" + ">> ?+ .clk_delays = NULL,\n" + ">> ?+ .can_calibrate = true,\n" + ">> ??};\n" ">>\n" - ">> \302\240\302\240static const struct of_device_id sunxi_mmc_of_match[] = {\n" - ">> \302\240@@ -1004,6 +1069,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"allwinner,sun5i-a13-mmc\", .data = &sun5i_a13_cfg },\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"allwinner,sun7i-a20-mmc\", .data = &sun7i_a20_cfg },\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"allwinner,sun9i-a80-mmc\", .data = &sun9i_a80_cfg },\n" - ">> \302\240+ { .compatible = \"allwinner,sun50i-a64-mmc\", .data = &sun50i_a64_cfg },\n" - ">> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ /* sentinel */ }\n" - ">> \302\240\302\240};\n" - ">> \302\240\302\240MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);\n" - "\n" - "_______________________________________________\n" - "linux-arm-kernel mailing list\n" - "linux-arm-kernel@lists.infradead.org\n" - http://lists.infradead.org/mailman/listinfo/linux-arm-kernel + ">> ??static const struct of_device_id sunxi_mmc_of_match[] = {\n" + ">> ?@@ -1004,6 +1069,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {\n" + ">> ??????????{ .compatible = \"allwinner,sun5i-a13-mmc\", .data = &sun5i_a13_cfg },\n" + ">> ??????????{ .compatible = \"allwinner,sun7i-a20-mmc\", .data = &sun7i_a20_cfg },\n" + ">> ??????????{ .compatible = \"allwinner,sun9i-a80-mmc\", .data = &sun9i_a80_cfg },\n" + ">> ?+ { .compatible = \"allwinner,sun50i-a64-mmc\", .data = &sun50i_a64_cfg },\n" + ">> ??????????{ /* sentinel */ }\n" + ">> ??};\n" + >> ??MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); -60ff1fa2ba0ad977398e00d15136d805077b50496f074e9c3c0f97be5d261df3 +d4b6d5b41c9c5c4ca194cc94e07167d5504dc0113ecca7a4d93995e92b26ee0b
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