From: cyril@ti.com (Cyril Chemparathy)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 RESEND 13/17] ARM: LPAE: factor out T1SZ and TTBR1 computations
Date: Mon, 24 Sep 2012 10:58:40 -0400 [thread overview]
Message-ID: <50607520.7090103@ti.com> (raw)
In-Reply-To: <20120924144531.GI23298@arm.com>
On 9/24/2012 10:45 AM, Catalin Marinas wrote:
> On Fri, Sep 21, 2012 at 04:56:11PM +0100, Cyril Chemparathy wrote:
>> This patch moves the TTBR1 offset calculation and the T1SZ calculation out
>> of the TTB setup assembly code. This should not affect functionality in
>> any way, but improves code readability as well as readability of subsequent
>> patches in this series.
>>
>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>> Acked-by: Nicolas Pitre <nico@linaro.org>
>> ---
>> arch/arm/include/asm/pgtable-3level-hwdef.h | 10 ++++++++++
>> arch/arm/mm/proc-v7-3level.S | 16 ++++------------
>> 2 files changed, 14 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
>> index d795282..b501650 100644
>> --- a/arch/arm/include/asm/pgtable-3level-hwdef.h
>> +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
>> @@ -74,4 +74,14 @@
>> #define PHYS_MASK_SHIFT (40)
>> #define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1)
>>
>> +#if defined CONFIG_VMSPLIT_2G
>> +#define TTBR1_OFFSET (1 << 4) /* skip two L1 entries */
>
> I know that was my code but I'm wondering why the (1<<4) rather than
> just a plain 16.
>
... to test my admittedly limited mental arithmetic skills, I'm
guessing? :-)
Will modify.
>> +#elif defined CONFIG_VMSPLIT_3G
>> +#define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */
>> +#else
>> +#define TTBR1_OFFSET 0
>> +#endif
>> +
>> +#define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16)
>
> You could also move the comment about TxSZ in proc-v7-3level.S, it makes
> it easier to figure out why TTBR1_SIZE is defined this way.
>
Sure. Fixed for v4 of this series.
>> --- a/arch/arm/mm/proc-v7-3level.S
>> +++ b/arch/arm/mm/proc-v7-3level.S
>> @@ -128,18 +128,10 @@ ENDPROC(cpu_v7_set_pte_ext)
>> * booting secondary CPUs would end up using TTBR1 for the identity
>> * mapping set up in TTBR0.
>> */
>
> Higher up in this file there is a cmp with a "branch below" comment. You
> should remove that as well since the 9001 branch was removed.
>
Fixed for v4 of this series.
--
Thanks
- Cyril
next prev parent reply other threads:[~2012-09-24 14:58 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-21 15:55 [PATCH v3 RESEND 00/17] LPAE fixes and extensions for Keystone Cyril Chemparathy
2012-09-21 15:55 ` Cyril Chemparathy
2012-09-21 15:55 ` [PATCH v3 RESEND 01/17] ARM: add mechanism for late code patching Cyril Chemparathy
2012-09-21 15:55 ` Cyril Chemparathy
2012-09-22 15:10 ` Nicolas Pitre
2012-09-22 15:10 ` Nicolas Pitre
2012-09-22 21:41 ` Cyril Chemparathy
2012-09-22 21:41 ` Cyril Chemparathy
2012-09-24 12:06 ` Dave Martin
2012-09-24 12:06 ` Dave Martin
2012-09-24 14:49 ` Cyril Chemparathy
2012-09-24 14:49 ` Cyril Chemparathy
2012-09-24 15:54 ` Dave Martin
2012-09-24 15:54 ` Dave Martin
2012-09-21 15:56 ` [PATCH v3 RESEND 02/17] ARM: add self test for runtime patch mechanism Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-21 15:56 ` [PATCH v3 RESEND 03/17] ARM: use late patch framework for phys-virt patching Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-21 15:56 ` [PATCH v3 RESEND 04/17] ARM: LPAE: use phys_addr_t on virt <--> phys conversion Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 13:09 ` Catalin Marinas
2012-09-24 13:57 ` Cyril Chemparathy
2012-09-21 15:56 ` [PATCH v3 RESEND 05/17] ARM: LPAE: support 64-bit virt_to_phys patching Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-22 15:24 ` Nicolas Pitre
2012-09-22 15:24 ` Nicolas Pitre
2012-09-24 15:13 ` Catalin Marinas
2012-09-24 15:56 ` Nicolas Pitre
2012-09-24 20:59 ` Cyril Chemparathy
2012-09-24 21:20 ` Nicolas Pitre
2012-09-24 21:52 ` Catalin Marinas
2012-09-24 22:32 ` Nicolas Pitre
2012-09-24 22:40 ` Russell King - ARM Linux
2012-09-24 22:53 ` Cyril Chemparathy
2012-09-24 23:03 ` Nicolas Pitre
2012-09-24 23:08 ` Russell King - ARM Linux
2012-09-24 22:55 ` Nicolas Pitre
2012-09-25 12:55 ` Dave Martin
2012-09-25 13:53 ` Catalin Marinas
2012-09-24 21:53 ` Cyril Chemparathy
2012-09-24 22:06 ` Russell King - ARM Linux
2012-09-24 16:31 ` Dave Martin
2012-09-24 16:31 ` Dave Martin
2012-09-24 16:51 ` Nicolas Pitre
2012-09-24 16:51 ` Nicolas Pitre
2012-09-21 15:56 ` [PATCH v3 RESEND 06/17] ARM: LPAE: use signed arithmetic for mask definitions Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 13:09 ` Catalin Marinas
2012-09-24 13:54 ` Russell King - ARM Linux
2012-09-24 13:54 ` Russell King - ARM Linux
2012-09-21 15:56 ` [PATCH v3 RESEND 07/17] ARM: LPAE: use phys_addr_t in alloc_init_pud() Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 13:10 ` Catalin Marinas
2012-09-21 15:56 ` [PATCH v3 RESEND 08/17] ARM: LPAE: use phys_addr_t in free_memmap() Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 13:29 ` Catalin Marinas
2012-09-24 13:41 ` Russell King - ARM Linux
2012-09-24 15:09 ` Cyril Chemparathy
2012-09-24 15:22 ` Russell King - ARM Linux
2012-09-24 16:41 ` Cyril Chemparathy
2012-09-24 16:51 ` Catalin Marinas
2012-09-24 17:06 ` Cyril Chemparathy
2012-09-24 17:14 ` Russell King - ARM Linux
2012-09-25 13:08 ` Catalin Marinas
2012-09-25 13:30 ` Russell King - ARM Linux
2012-09-24 16:55 ` Russell King - ARM Linux
2012-09-24 17:03 ` Catalin Marinas
2012-09-21 15:56 ` [PATCH v3 RESEND 09/17] ARM: LPAE: use phys_addr_t for initrd location and size Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 13:30 ` Catalin Marinas
2012-09-24 13:38 ` Russell King - ARM Linux
2012-09-24 13:38 ` Russell King - ARM Linux
2012-09-24 14:00 ` Cyril Chemparathy
2012-09-24 14:00 ` Cyril Chemparathy
2012-09-21 15:56 ` [PATCH v3 RESEND 10/17] ARM: LPAE: use phys_addr_t in switch_mm() Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 14:05 ` Catalin Marinas
2012-09-24 14:32 ` Cyril Chemparathy
2012-09-21 15:56 ` [PATCH v3 RESEND 11/17] ARM: LPAE: use 64-bit accessors for TTBR registers Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 14:10 ` Catalin Marinas
2012-09-21 15:56 ` [PATCH v3 RESEND 12/17] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 14:16 ` Catalin Marinas
2012-09-21 15:56 ` [PATCH v3 RESEND 13/17] ARM: LPAE: factor out T1SZ and TTBR1 computations Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 14:45 ` Catalin Marinas
2012-09-24 14:58 ` Cyril Chemparathy [this message]
2012-09-21 15:56 ` [PATCH v3 RESEND 14/17] ARM: LPAE: accomodate >32-bit addresses for page table base Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 15:17 ` Catalin Marinas
2012-09-21 15:56 ` [PATCH v3 RESEND 15/17] ARM: mm: use physical addresses in highmem sanity checks Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-24 15:18 ` Catalin Marinas
2012-09-21 15:56 ` [PATCH v3 RESEND 16/17] ARM: mm: cleanup checks for membank overlap with vmalloc area Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
2012-09-21 15:56 ` [PATCH v3 RESEND 17/17] ARM: mm: clean up membank size limit checks Cyril Chemparathy
2012-09-21 15:56 ` Cyril Chemparathy
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