From: Peter Barada <peter.barada@gmail.com>
To: "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>
Subject: Per-partition NAND ECC?
Date: Mon, 24 Sep 2012 11:04:40 -0400 [thread overview]
Message-ID: <50607688.6090601@gmail.com> (raw)
On the OMAP3 parts the bootrom has a hard requirement of using 1-bit
Hamming ECC to read the 2nd stage bootloader(x-loader / SPL) out of the
first four blocks of NAND. The Micron MT29C4G48MAZAPAKQ5 PoP part we're
using requires 4-bit ECC for all the other NAND blocks to maintain an
acceptable UBER.
Currently this wasn't a problem since I could use u-boot to update the
2nd stage bootloader. I now have a need to be able to update the 2nd
stage bootloader from Linux only so I need the ability to write/read
pages in a NAND partition with a different ECC method than that
specified over the device. I think it would be more elegant to solve
this by allowing partition entry/mtdparts to specify its ECC
methodology, track that as part of the MTD device down into the nand
driver, and switch ECC methods/entrypoints as it changes.
Does anyone have suggestions on how to best approach this?
Thanks in advance!
--
Peter Barada
peter.barada@gmail.com
next reply other threads:[~2012-09-24 15:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-24 15:04 Peter Barada [this message]
2012-09-24 15:29 ` Per-partition NAND ECC? Andreas Bießmann
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