From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([208.118.235.92]:43428)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1THNVj-0005qv-U2
	for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:28:52 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1THNVj-0001wr-43
	for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:28:51 -0400
Received: from mail-pb0-f45.google.com ([209.85.160.45]:50304)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1THNVi-0001vt-Tn
	for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:28:51 -0400
Received: by pbbrp2 with SMTP id rp2so4305853pbb.4
	for <qemu-devel@nongnu.org>; Thu, 27 Sep 2012 16:28:50 -0700 (PDT)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <5064E12F.5040308@twiddle.net>
Date: Thu, 27 Sep 2012 16:28:47 -0700
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1348766397-20731-1-git-send-email-rth@twiddle.net>
	<1348766397-20731-3-git-send-email-rth@twiddle.net>
	<20120927232015.GN23819@ohm.aurel32.net>
In-Reply-To: <20120927232015.GN23819@ohm.aurel32.net>
Content-Type: text/plain; charset=ISO-8859-15
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 2/7] tcg: Optimize add2 + sub2
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: qemu-devel@nongnu.org

On 09/27/2012 04:20 PM, Aurelien Jarno wrote:
> I understand that we can't easily insert an instruction, so the
> limitation comes from here, but is it really something happening often?

It will certainly appear sometimes.  E.g. s390x has an add immediate
instruction that does exactly: r1 += imm16 << 32.

Or did you mean specifically the full constant being folded?  That
would happen quite a bit more often.  That you can see with most any
64-bit RISC guest when they attempt to generate a constant from 
addition primitives instead of logical primitives.

For a 32-bit host, we've already decomposed logical primitives to 32-bit
operations.  And we can constant-fold through all of those.  But when
addition comes into play, we can't constant-fold through add2.


r~