From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLZ8d-0004Ou-Cx for qemu-devel@nongnu.org; Tue, 09 Oct 2012 08:42:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLZ8R-0004Jo-PL for qemu-devel@nongnu.org; Tue, 09 Oct 2012 08:42:19 -0400 Received: from cantor2.suse.de ([195.135.220.15]:42523 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLZ8R-0004JY-Fk for qemu-devel@nongnu.org; Tue, 09 Oct 2012 08:42:07 -0400 Message-ID: <50741B9A.90803@suse.de> Date: Tue, 09 Oct 2012 14:42:02 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 4/4] zynq_slcr: Implement CPU reset and halting List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: linnj@xilinx.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, john.williams@petalogix.com, edgar.iglesias@gmail.com Am 04.10.2012 02:16, schrieb Peter Crosthwaite: > From: Peter A. G. Crosthwaite >=20 > Implement the CPU reset and halt functions of the A9_CPU_RST_CTRL regis= ter > (offset 0x244). >=20 > Signed-off-by: Peter A. G. Crosthwaite > --- >=20 > hw/zynq_slcr.c | 18 ++++++++++++++++++ > 1 files changed, 18 insertions(+), 0 deletions(-) >=20 > diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c > index 6eafad5..c1922fc 100644 > --- a/hw/zynq_slcr.c > +++ b/hw/zynq_slcr.c > @@ -116,6 +116,9 @@ typedef enum { > RESET_MAX > } ResetValues; > =20 > +#define A9_CPU_RST_CTRL_RST_SHIFT 0 > +#define A9_CPU_RST_CTRL_CLKSTOP_SHIFT 4 > + > typedef struct { > SysBusDevice busdev; > MemoryRegion iomem; > @@ -346,6 +349,7 @@ static void zynq_slcr_write(void *opaque, target_ph= ys_addr_t offset, > uint64_t val, unsigned size) > { > ZynqSLCRState *s =3D (ZynqSLCRState *)opaque; > + int i; > =20 > DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val); > =20 > @@ -400,6 +404,20 @@ static void zynq_slcr_write(void *opaque, target_p= hys_addr_t offset, > goto bad_reg; > } > s->reset[(offset - 0x200) / 4] =3D val; > + if (offset - 0x200 =3D=3D A9_CPU * 4) { /* CPU Reset */ > + for (i =3D 0; i < NUM_CPUS && s->cpus[i]; ++i) { > + bool is_rst =3D val & (1 << (A9_CPU_RST_CTRL_RST_S= HIFT + i)); > + bool is_clkstop =3D val & > + (1 << (A9_CPU_RST_CTRL_CLKSTOP_SHI= FT + i)); > + if (is_rst) { > + CPU_GET_CLASS(CPU(s->cpus[i]))->reset(CPU(s->c= pus[i])); Isn't that just cpu_reset(CPU(s->cpus[i]));? Please prefer that over open-coding. Thanks, Andreas > + DB_PRINT("resetting cpu %d\n", i); > + } > + s->cpus[i]->env.halted =3D is_rst || is_clkstop; > + DB_PRINT("%shalting cpu %d\n", s->cpus[i]->env.hal= ted ? > + "" : "un", i); > + } > + } > break; > case 0x300: > s->apu_ctrl =3D val; >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg