From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59648) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TM3KS-00075n-D0 for qemu-devel@nongnu.org; Wed, 10 Oct 2012 16:56:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TM3KO-0007sH-9J for qemu-devel@nongnu.org; Wed, 10 Oct 2012 16:56:32 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:42960) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TM3KN-0007qY-Ve for qemu-devel@nongnu.org; Wed, 10 Oct 2012 16:56:28 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so365543dad.4 for ; Wed, 10 Oct 2012 13:56:27 -0700 (PDT) Sender: Richard Henderson Message-ID: <5075E0F9.30100@twiddle.net> Date: Wed, 10 Oct 2012 13:56:25 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1349814748-22552-1-git-send-email-aurelien@aurel32.net> <1349814748-22552-4-git-send-email-aurelien@aurel32.net> In-Reply-To: <1349814748-22552-4-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/4] tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org On 10/09/2012 01:32 PM, Aurelien Jarno wrote: > Remove suboptimal register shifting in qemu_ld/st ops, introduced at the > CONFIG_TCG_PASS_AREG0 time. > > As mem_idx is now loaded in register R58/R59 for the slow path, we have > to make sure to do it last, to not add additional register constraints. > > Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson r~