Re: [PATCH 0/2] KVM: PPC: Support ioeventfd

[Alexander Graf <agraf@suse.de>]

On 10/16/2012 03:47 PM, Avi Kivity wrote:
> On 10/16/2012 01:06 PM, Alexander Graf wrote:
>> On 16.10.2012, at 13:01, Avi Kivity wrote:
>>
>>> On 10/16/2012 12:59 PM, Alexander Graf wrote:
>>>> On 16.10.2012, at 12:56, Avi Kivity wrote:
>>>>
>>>>> On 10/15/2012 02:02 PM, Alexander Graf wrote:
>>>>>> In order to support vhost, we need to be able to support ioeventfd.
>>>>>>
>>>>>> This patch set adds support for ioeventfd to PPC and makes it possible to
>>>>>> do so without implementing irqfd along the way, as it requires an in-kernel
>>>>>> irqchip which we don't have yet.
>>>>> It's not strictly required.  You have an interrupt line leading to the
>>>>> core, no?  You could have your irqfd trigger that.
>>>> The irqfd code in KVM directly triggers the in-kernel irqchip. That's what this patch set is cleaning up: enable you to build ioeventfd support without in-kernel irqchip irqfd support.
>>>>
>>>> Vhost can work without in-kernel irqchip too, by listening to an eventfd (iiuc) in user space. That path works just fine with these patches applied.
>>> That's all true but it wasn't my point.  I was asking whether you can
>>> enable irqfd without in-kernel irqchip.  If your irq input is edge
>>> triggered then it's trivial.  If it's level triggered then you can use
>>> the new resampling irqfd.
>> I'm not sure I fully grasp what you're trying to say :).
>>
>> We have a single interrupt line on the core. So whenever any external interrupt gets injected (same thing for MSI), we need to go to the MPIC / XICS and ask it which line is active.
> Couldn't you attach that payload to the irqfd?  On x86 an irqfd is
> associated with a gsi, and a gsi with extra information, including all
> that is needed to queue an MSI.
>
>> So yes, we could create a direct fd channel between vhost and the user space MPIC, but it wouldn't buy us anything. The interrupt injection path would be as long as it is with the current mechanism.
>>
> If there is a lot of prioritization and/or queuing logic, then yes.  But
> what about MSI?  Doesn't that have a direct path?

Nope. Well, yes, in a certain special case where the MPIC pushes the 
interrupt vector on interrupt delivery into a special register. But not 
for the "normal" case.


Alex