From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Egger Subject: [PATCH] vMCE: Implement AMD MSRs Date: Wed, 17 Oct 2012 12:41:03 +0200 Message-ID: <507E8B3F.8030801@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------030605020302030609080700" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org --------------030605020302030609080700 Content-Type: text/plain; charset="ISO-8859-15" Content-Transfer-Encoding: 7bit Implement AMD MSRs for vMCE Signed-off-by: Christoph Egger -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 --------------030605020302030609080700 Content-Type: text/plain; charset="us-ascii"; name="xen_vmce.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="xen_vmce.diff" Content-Description: xen_vmce.diff # User Christoph Egger # Date 1350465050 -7200 implement AMD MSRs for vMCE Signed-off-by: Christoph Egger diff -r 9181f580bc3f -r 7d79c4a86be5 xen/arch/x86/cpu/mcheck/amd_f10.c --- a/xen/arch/x86/cpu/mcheck/amd_f10.c +++ b/xen/arch/x86/cpu/mcheck/amd_f10.c @@ -106,24 +106,43 @@ enum mcheck_type amd_f10_mcheck_init(str /* amd specific MCA MSR */ int vmce_amd_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) { - switch (msr) { - case MSR_F10_MC4_MISC1: - case MSR_F10_MC4_MISC2: - case MSR_F10_MC4_MISC3: - break; - } + switch (msr) { + case MSR_F10_MC4_MISC1: /* DRAM error type */ + v->arch.vmce.bank[1].mci_misc = val; + mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val); + break; + case MSR_F10_MC4_MISC2: /* Link error type */ + case MSR_F10_MC4_MISC3: /* L3 cache error type */ + /* ignore write: we do not emulate link and l3 cache errors + * to the guest. + */ + mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val); + break; + default: + return 0; + } - return 1; + return 1; } int vmce_amd_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) { - switch (msr) { - case MSR_F10_MC4_MISC1: - case MSR_F10_MC4_MISC2: - case MSR_F10_MC4_MISC3: - break; - } + switch (msr) { + case MSR_F10_MC4_MISC1: /* DRAM error type */ + *val = v->arch.vmce.bank[1].mci_misc; + mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val); + break; + case MSR_F10_MC4_MISC2: /* Link error type */ + case MSR_F10_MC4_MISC3: /* L3 cache error type */ + /* we do not emulate link and l3 cache + * errors to the guest. + */ + *val = 0; + mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val); + break; + default: + return 0; + } - return 1; + return 1; } --------------030605020302030609080700 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --------------030605020302030609080700--