[U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53

[Stefano Babic <sbabic@denx.de>]

Am 15/10/2012 17:37, schrieb Fabio Estevam:
> Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
> 
> Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz 
> instead.
> 
> Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
> at 1080p because the IPU clock cannot reach the requested frequency.
> 
> Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its 
> maximum frequency.
> 
> Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
> bit to allow easier comparison with the original clock setup from FSL U-boot.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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