From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Wed, 17 Oct 2012 17:23:55 +0000 Subject: Re: [PATCH 0/2] KVM: PPC: Support ioeventfd Message-Id: <507EE9AB.8070904@suse.de> List-Id: References: <1350302566-28889-1-git-send-email-agraf@suse.de> <507D3D4D.2090507@redhat.com> <507D3E91.6070909@redhat.com> <3E4E65FD-8C9E-481A-B2C7-D1E7B23F362C@suse.de> <507D656C.3020502@redhat.com> <507D7413.1000506@suse.de> <507EC5AF.2080907@redhat.com> In-Reply-To: <507EC5AF.2080907@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Avi Kivity Cc: KVM list , kvm-ppc@vger.kernel.org On 10/17/2012 04:50 PM, Avi Kivity wrote: > On 10/16/2012 04:49 PM, Alexander Graf wrote: > >>> If there is a lot of prioritization and/or queuing logic, then yes. But >>> what about MSI? Doesn't that have a direct path? >> Nope. Well, yes, in a certain special case where the MPIC pushes the >> interrupt vector on interrupt delivery into a special register. But not >> for the "normal" case. > Ok. The patches are fine then, but would be good to add the PIO check. Yup, will do as a separate patch. Alex From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [PATCH 0/2] KVM: PPC: Support ioeventfd Date: Wed, 17 Oct 2012 19:23:55 +0200 Message-ID: <507EE9AB.8070904@suse.de> References: <1350302566-28889-1-git-send-email-agraf@suse.de> <507D3D4D.2090507@redhat.com> <507D3E91.6070909@redhat.com> <3E4E65FD-8C9E-481A-B2C7-D1E7B23F362C@suse.de> <507D656C.3020502@redhat.com> <507D7413.1000506@suse.de> <507EC5AF.2080907@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: KVM list , kvm-ppc@vger.kernel.org To: Avi Kivity Return-path: In-Reply-To: <507EC5AF.2080907@redhat.com> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 10/17/2012 04:50 PM, Avi Kivity wrote: > On 10/16/2012 04:49 PM, Alexander Graf wrote: > >>> If there is a lot of prioritization and/or queuing logic, then yes. But >>> what about MSI? Doesn't that have a direct path? >> Nope. Well, yes, in a certain special case where the MPIC pushes the >> interrupt vector on interrupt delivery into a special register. But not >> for the "normal" case. > Ok. The patches are fine then, but would be good to add the PIO check. Yup, will do as a separate patch. Alex