Re: Tegra DRM with HDMI support (\o/)

[Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]

On 10/17/2012 02:08 PM, Jon Mayo wrote:
> Stephen Warren wrote at Wednesday, October 17, 2012 12:42 PM:
>> On 10/17/2012 01:12 PM, Thierry Reding wrote:
>>> On Wed, Oct 17, 2012 at 11:04:05AM -0700, Jon Mayo wrote:
...
>>>> On T30, HDMI will work with pll_d, but I'm tipping my hand and
>>>> telling you that if you always use pll_d2 you won't have to mess
>>>> with this code in the next few chips. :)
>>>
>>> If we make this configurable in the device tree, we could provide
>>> both the "hdmi" and "base-clock" clocks, where base-clock defaults
>>> to pll_d or pll_d2 depending on the Tegra generation. If some board
>>> requires a more exotic setup it can override the clocks in the
>>> board DTS.
>>
>> I think if the parenting is going to be static, lets not have tegradrm
>> do it, but rather encode it into one of
>> arch/arm/mach-tegra/{common,board-dt-tegra[23]0}.c. Eventually, we
>> wish to replace the clock setup tables in those files with tables in
>> device tree, so they can differ easily per-board, which would also
>> handle the DSI situation well.
> 
> Well it's not entirely static. The clock parent should depend on the
> output type. rather than on which display controller you are using.
> Each DC can be configured for various output types. The output types
> can be represented in device-tree if you wish to have them fixed (I'd
> interpret it as a default rather than a fixed setting).

(Jon, the lack of line-wrapping makes your email a little hard to read)

Yes, that makes sense. We should leave the clock definitions up to the
OR driver rather than statically set them up based on the DC then.

Once clocks come from DT, that probably requires each OR to define two
clocks; the peripheral clock and the parent PLL, e.g.:

clocks = <&car CLK_HDMI> <&car CLK_PLL_D>;
clock-names = "output", "parent";

... and then do a clk_set_parent() when being activated.