From: Richard Henderson <rth@twiddle.net>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] Revert "target-sparc: Make cpu_dst local to OP=2 insns"
Date: Sun, 21 Oct 2012 08:48:52 +1000 [thread overview]
Message-ID: <50832A54.5020609@twiddle.net> (raw)
In-Reply-To: <1350744508-7066-1-git-send-email-aurelien@aurel32.net>
On 2012-10-21 00:48, Aurelien Jarno wrote:
> I am not sure it is the real problem, but at least the optimization of
> using the destination register as a temporary is wrong when the
> instruction might trigger an exception. In that case the result is
> written to the destination register while it should have not.
>
> This reverts commit 5793f2a47e201d251856c7956d6f7907ec0d9f1f.
Which insn might trigger an exception? Most OP=2 insns don't. There's
divide, but that's done out-of-line, so the assignment to dst does not
happen before the exception...
Is this sparc64? I assume so, since I did test sparc32...
r~
next prev parent reply other threads:[~2012-10-20 22:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-20 14:48 [Qemu-devel] [PATCH] Revert "target-sparc: Make cpu_dst local to OP=2 insns" Aurelien Jarno
2012-10-20 22:48 ` Richard Henderson [this message]
2012-10-20 23:17 ` Aurelien Jarno
2012-10-21 21:29 ` Richard Henderson
2012-10-21 22:25 ` Aurelien Jarno
2012-10-22 22:15 ` Aurelien Jarno
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