From: Christoph Egger <Christoph.Egger@amd.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Subject: Re: [PATCH] x86/MCE: Implement clearbank callback for AMD
Date: Thu, 25 Oct 2012 10:18:07 +0200 [thread overview]
Message-ID: <5088F5BF.2090603@amd.com> (raw)
In-Reply-To: <5087F8B902000078000A3F38@nat28.tlf.novell.com>
On 10/24/12 14:18, Jan Beulich wrote:
>>>> On 12.10.12 at 16:46, Christoph Egger <Christoph.Egger@amd.com> wrote:
>> +static int k8_need_clearbank_scan(enum mca_source who, uint64_t status)
>> +{
>> + switch (who) {
>> + case MCA_MCE_SCAN:
>> + case MCA_MCE_HANDLER:
>> + break;
>> + default:
>> + return 1;
>> + }
>> +
>> + /* For fatal error, it shouldn't be cleared so that sticky bank
>> + * have chance to be handled after reboot by polling.
>> + */
>> + if ( (status & MCi_STATUS_UC) && (status & MCi_STATUS_PCC) )
>> + return 0;
>> + /* Spurious need clear bank */
>> + if ( !(status & MCi_STATUS_OVER)
>> + && (status & MCi_STATUS_UC) && !(status & MCi_STATUS_EN))
>> + return 1;
>> +
>> + return 1;
>> }
>
> So what's the purpose of first conditionally returning 1, and then
> also doing so unconditionally? Do anticipate to insert code between
> the two parts within the very near future? Otherwise I'd drop the
> whole if() construct.
This function is derived from intel_need_clearbank_scan().
I just took over the relevant parts for AMD.
Christoph
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next prev parent reply other threads:[~2012-10-25 8:18 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-12 14:46 [PATCH] x86/MCE: Implement clearbank callback for AMD Christoph Egger
2012-10-19 13:11 ` Christoph Egger
2012-10-19 14:59 ` Jan Beulich
2012-10-24 12:18 ` Jan Beulich
2012-10-25 8:18 ` Christoph Egger [this message]
2012-10-25 8:55 ` Jan Beulich
2012-10-25 9:29 ` Christoph Egger
2012-10-25 10:03 ` Jan Beulich
2012-10-25 10:13 ` Christoph Egger
2012-10-25 10:23 ` Christoph Egger
2012-10-25 10:28 ` Jan Beulich
2012-10-25 10:30 ` Christoph Egger
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