From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Egger Subject: Re: [PATCH] MCE: support cpu notification chain Date: Thu, 25 Oct 2012 16:45:44 +0200 Message-ID: <50895098.50405@amd.com> References: <5089449C.7020700@amd.com> <5089646102000078000A48DA@nat28.tlf.novell.com> <50894A2D.8030007@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------030003000508070003020702" Return-path: In-Reply-To: <50894A2D.8030007@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org --------------030003000508070003020702 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit On 10/25/12 16:18, Christoph Egger wrote: > On 10/25/12 16:10, Jan Beulich wrote: >>>>> On 25.10.12 at 15:54, Christoph Egger wrote: >>> Add support for cpu notification chain. >>> This is useful with nested virtualization when Xen >>> runs as l1 hypervisor. >>> This cleans up mce initialization cleanup as a side-effect. >> >> Did you notice the fix I had done to your earlier patch before >> committing c/s 26106:1883c1d29de9? With the change here, >> mce_clear_banks will get allocated twice (once in generic code >> and once in AMD specific code), leaking one instance. > > Ugh... must be a merge botch. Updated patch attached. Signed-off-by: Christoph Egger -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 --------------030003000508070003020702 Content-Type: text/plain; charset="us-ascii"; name="xen_mce_init.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="xen_mce_init.diff" Content-Description: xen_mce_init.diff diff -r 7abb25095de0 xen/arch/x86/cpu/mcheck/mce.c --- a/xen/arch/x86/cpu/mcheck/mce.c Thu Oct 25 13:15:19 2012 +0200 +++ b/xen/arch/x86/cpu/mcheck/mce.c Thu Oct 25 15:13:24 2012 +0200 @@ -560,30 +560,6 @@ void mcheck_mca_clearbanks(struct mca_ba } } -static enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci) -{ - enum mcheck_type rc = mcheck_none; - - switch (ci->x86) { - case 6: - rc = amd_k7_mcheck_init(ci); - break; - - default: - /* Assume that machine check support is available. - * The minimum provided support is at least the K8. */ - case 0xf: - rc = amd_k8_mcheck_init(ci); - break; - - case 0x10 ... 0x17: - rc = amd_f10_mcheck_init(ci); - break; - } - - return rc; -} - /*check the existence of Machine Check*/ int mce_available(struct cpuinfo_x86 *c) { @@ -774,7 +750,7 @@ void mcheck_init(struct cpuinfo_x86 *c, switch (c->x86_vendor) { case X86_VENDOR_AMD: - inited = amd_mcheck_init(c); + inited = amd_mcheck_init(c, bsp); break; case X86_VENDOR_INTEL: diff -r 7abb25095de0 xen/arch/x86/cpu/mcheck/mce.h --- a/xen/arch/x86/cpu/mcheck/mce.h Thu Oct 25 13:15:19 2012 +0200 +++ b/xen/arch/x86/cpu/mcheck/mce.h Thu Oct 25 15:13:24 2012 +0200 @@ -39,10 +39,7 @@ enum mcheck_type { }; /* Init functions */ -enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c); -enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c); -enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c); - +enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp); enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp); void intel_mcheck_timer(struct cpuinfo_x86 *c); diff -r 7abb25095de0 xen/arch/x86/cpu/mcheck/mce_amd.c --- a/xen/arch/x86/cpu/mcheck/mce_amd.c Thu Oct 25 13:15:19 2012 +0200 +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c Thu Oct 25 15:13:24 2012 +0200 @@ -19,6 +19,7 @@ #include #include +#include #include @@ -98,3 +99,53 @@ mc_amd_addrcheck(uint64_t status, uint64 BUG(); return 0; } + +static int +amd_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) +{ + int rc = 0; + + switch (action) { + case CPU_DYING: + clear_in_cr4(X86_CR4_MCE); + break; + default: + break; + } + + return notifier_from_errno(rc); +} + +static struct notifier_block cpu_nfb = { + .notifier_call = amd_cpu_callback +}; + +enum mcheck_type +amd_mcheck_init(struct cpuinfo_x86 *ci, bool_t bsp) +{ + enum mcheck_type rc = mcheck_none; + + if (bsp) { + /* Early MCE initialization for BSP. */ + register_cpu_notifier(&cpu_nfb); + } + + switch (ci->x86) { + case 6: + rc = amd_k7_mcheck_init(ci); + break; + + default: + /* Assume that machine check support is available. + * The minimum provided support is at least the K8. */ + case 0xf: + rc = amd_k8_mcheck_init(ci); + break; + + case 0x10 ... 0x17: + rc = amd_f10_mcheck_init(ci); + break; + } + + return rc; +} diff -r 7abb25095de0 xen/arch/x86/cpu/mcheck/mce_amd.h --- a/xen/arch/x86/cpu/mcheck/mce_amd.h Thu Oct 25 13:15:19 2012 +0200 +++ b/xen/arch/x86/cpu/mcheck/mce_amd.h Thu Oct 25 15:13:24 2012 +0200 @@ -1,6 +1,10 @@ #ifndef _MCHECK_AMD_H #define _MCHECK_AMD_H +enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c); + int mc_amd_recoverable_scan(uint64_t status); int mc_amd_addrcheck(uint64_t status, uint64_t misc, int addrtype); --------------030003000508070003020702 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --------------030003000508070003020702--