From: Gerd Hoffmann <kraxel@redhat.com>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: vineshp@xilinx.com, peter.maydell@linaro.org,
qemu-devel@nongnu.org, john.williams@xilinx.com,
edgar.iglesias@gmail.com, afaerber@suse.de
Subject: Re: [Qemu-devel] [PATCH v2 11/11] usb/ehci: Put RAM in undefined MMIO regions
Date: Mon, 29 Oct 2012 08:44:47 +0100 [thread overview]
Message-ID: <508E33EF.9080809@redhat.com> (raw)
In-Reply-To: <CAEgOgz6N+pzRi1UiYyzKB+-y6eTJVsr0FkS_R8wF1aQoY4dF7Q@mail.gmail.com>
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On 10/27/12 02:42, Peter Crosthwaite wrote:
>> Any chance the access you are seeing is at offset 0x68?
>
> 0x1a8. which for the opregbase + 0x068 for zynq so probably what you
> are thinking about.
Does the attached patch help?
cheers,
Gerd
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>From 6a131b1476640c07317a6f44b5bb54ec53974414 Mon Sep 17 00:00:00 2001
From: Gerd Hoffmann <kraxel@redhat.com>
Date: Mon, 29 Oct 2012 08:32:47 +0100
Subject: [PATCH] ehci: set extended capability pointer on pci only
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
hw/usb/hcd-ehci.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index a07beff..a35cbf2 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -2792,7 +2792,6 @@ static void usb_ehci_initfn(EHCIState *s, DeviceState *dev, EHCIInfo *ei)
s->caps[0x06] = 0x00;
s->caps[0x07] = 0x00;
s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
- s->caps[0x09] = 0x68; /* EECP */
s->caps[0x0a] = 0x00;
s->caps[0x0b] = 0x00;
@@ -2880,6 +2879,8 @@ static int usb_ehci_pci_initfn(PCIDevice *dev)
s->irq = dev->irq[3];
s->dma = pci_dma_context(dev);
+ s->caps[0x09] = 0x68; /* EECP */
+
usb_ehci_initfn(s, DEVICE(dev), &c->ehci);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
--
1.7.1
prev parent reply other threads:[~2012-10-29 7:44 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-26 5:47 [Qemu-devel] [PATCH v2 00/11] Sysbus EHCI + Zynq USB Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 01/11] dma: Define dma_context_memory and use in sysbus-ohci Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 02/11] usb/ehci: Use class_data to init PCI variations Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 03/11] usb/ehci: parameterise the register region offsets Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 04/11] usb/ehci: Abstract away PCI DMA API Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 05/11] usb/ehci: seperate out PCIisms Peter Crosthwaite
2012-10-26 12:24 ` Gerd Hoffmann
2012-10-27 0:32 ` Peter Crosthwaite
2012-10-29 1:04 ` Peter Crosthwaite
2012-10-29 7:43 ` Gerd Hoffmann
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 06/11] usb/ehci: Add Sysbus Infrastructure Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 07/11] usb/ehci: Add Xilinx ps7 USB controller Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 08/11] xilinx_zynq: add USB controllers Peter Crosthwaite
2012-10-26 12:26 ` Gerd Hoffmann
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 09/11] usb/ehci: Guard definition of EHCI_DEBUG Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 10/11] usb/ehci: Debug mode compile fixes Peter Crosthwaite
2012-10-26 5:47 ` [Qemu-devel] [PATCH v2 11/11] usb/ehci: Put RAM in undefined MMIO regions Peter Crosthwaite
2012-10-26 8:37 ` Peter Maydell
2012-10-26 12:36 ` Gerd Hoffmann
2012-10-26 12:39 ` Peter Maydell
2012-10-27 16:08 ` Peter Crosthwaite
2012-10-27 0:42 ` Peter Crosthwaite
2012-10-29 7:44 ` Gerd Hoffmann [this message]
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