diff for duplicates of <50A3DF29.1070806@wwwdotorg.org> diff --git a/a/1.txt b/N1/1.txt index a2c7e0e..7a1b064 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -37,7 +37,7 @@ Git archaeology shows that the following commits are relevant, the first and last one in particular: > commit 9abafa021e223f04d6589ee2b977bbaf2e1f1367 -> Author: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Author: Stephen Warren <swarren@nvidia.com> > Date: Thu Apr 12 14:13:05 2012 -0600 > > ARM: tegra: change pll_p_out4's rate to 24MHz @@ -48,11 +48,11 @@ and last one in particular: > > Remove board-paz00.c's now-duplicate initialization of this clock. > -> Reported-by: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org> -> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Reported-by: Marc Dietrich <marvin24@gmx.de> +> Signed-off-by: Stephen Warren <swarren@nvidia.com> > > commit 7ff4db0967bd7d617c77dc5a66c0d95166277817 -> Author: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Author: Stephen Warren <swarren@nvidia.com> > Date: Fri Apr 20 16:58:18 2012 -0600 > > ARM: tegra: fix pclk rate @@ -62,10 +62,10 @@ and last one in particular: > dividers, the pclk rate needs to change in the same fashion, from 54MHz > to 60MHz. > -> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Stephen Warren <swarren@nvidia.com> > > commit 60f975b98cf41476ba0e156f7523b197b046cf2b -> Author: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Author: Stephen Warren <swarren@nvidia.com> > Date: Thu Apr 12 14:09:39 2012 -0600 > > ARM: tegra: reparent sclk to pll_c_out1 @@ -76,10 +76,10 @@ and last one in particular: > rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909..., > 600/6=100). > -> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Stephen Warren <swarren@nvidia.com> > > commit c8b62ab41f76218efca5e4baa5c22ef52a9fe3a5 -> Author: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Author: Allen Martin <amartin@nvidia.com> > Date: Fri Sep 10 09:17:33 2010 -0500 > > ARM: tegra: Add pllc clock init table @@ -94,7 +94,7 @@ and last one in particular: > to match the default rate of this PLL when the HW boots, and it's not > clear to me why 522 or 598MHz are more useful. > -> Signed-off-by: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> -> Signed-off-by: Olof Johansson <olofj-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> -> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Allen Martin <amartin@nvidia.com> +> Signed-off-by: Olof Johansson <olofj@chromium.org> +> Signed-off-by: Stephen Warren <swarren@nvidia.com> > [swarren: wrote commit description] diff --git a/a/content_digest b/N1/content_digest index babe3c1..f8e4047 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,14 +6,13 @@ "ref\020121114105406.GA31455@avionic-0098.mockup.avionic-design.de\0" "ref\050A3C485.7080704@wwwdotorg.org\0" "ref\050A3CAA3.2060908@nvidia.com\0" - "ref\050A3CAA3.2060908-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" - "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0" + "From\0Stephen Warren <swarren@wwwdotorg.org>\0" "Subject\0Re: [PATCH 1/2] ARM: tegra: Add Tegra20 host1x support\0" "Date\0Wed, 14 Nov 2012 11:12:57 -0700\0" - "To\0Terje Bergstr\303\266m <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>" - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" + "To\0Terje Bergstr\303\266m <tbergstrom@nvidia.com>\0" + "Cc\0Thierry Reding <thierry.reding@avionic-design.de>" + linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> + " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "On 11/14/2012 09:45 AM, Terje Bergstr\303\266m wrote:\n" @@ -55,7 +54,7 @@ "and last one in particular:\n" "\n" "> commit 9abafa021e223f04d6589ee2b977bbaf2e1f1367\n" - "> Author: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Author: Stephen Warren <swarren@nvidia.com>\n" "> Date: Thu Apr 12 14:13:05 2012 -0600\n" "> \n" "> ARM: tegra: change pll_p_out4's rate to 24MHz\n" @@ -66,11 +65,11 @@ "> \n" "> Remove board-paz00.c's now-duplicate initialization of this clock.\n" "> \n" - "> Reported-by: Marc Dietrich <marvin24-Mmb7MZpHnFY@public.gmane.org>\n" - "> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Reported-by: Marc Dietrich <marvin24@gmx.de>\n" + "> Signed-off-by: Stephen Warren <swarren@nvidia.com>\n" "> \n" "> commit 7ff4db0967bd7d617c77dc5a66c0d95166277817\n" - "> Author: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Author: Stephen Warren <swarren@nvidia.com>\n" "> Date: Fri Apr 20 16:58:18 2012 -0600\n" "> \n" "> ARM: tegra: fix pclk rate\n" @@ -80,10 +79,10 @@ "> dividers, the pclk rate needs to change in the same fashion, from 54MHz\n" "> to 60MHz.\n" "> \n" - "> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Stephen Warren <swarren@nvidia.com>\n" "> \n" "> commit 60f975b98cf41476ba0e156f7523b197b046cf2b\n" - "> Author: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Author: Stephen Warren <swarren@nvidia.com>\n" "> Date: Thu Apr 12 14:09:39 2012 -0600\n" "> \n" "> ARM: tegra: reparent sclk to pll_c_out1\n" @@ -94,10 +93,10 @@ "> rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,\n" "> 600/6=100).\n" "> \n" - "> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Stephen Warren <swarren@nvidia.com>\n" "> \n" "> commit c8b62ab41f76218efca5e4baa5c22ef52a9fe3a5\n" - "> Author: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Author: Allen Martin <amartin@nvidia.com>\n" "> Date: Fri Sep 10 09:17:33 2010 -0500\n" "> \n" "> ARM: tegra: Add pllc clock init table\n" @@ -112,9 +111,9 @@ "> to match the default rate of this PLL when the HW boots, and it's not\n" "> clear to me why 522 or 598MHz are more useful.\n" "> \n" - "> Signed-off-by: Allen Martin <amartin-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" - "> Signed-off-by: Olof Johansson <olofj-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>\n" - "> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Allen Martin <amartin@nvidia.com>\n" + "> Signed-off-by: Olof Johansson <olofj@chromium.org>\n" + "> Signed-off-by: Stephen Warren <swarren@nvidia.com>\n" > [swarren: wrote commit description] -4c11116ecab184dded0ea61454a980ca0d3b4e936d60c84f3065ce65fe4a7ea7 +31477c845a1263ef0dca1c7fb93be72982b6897642f28319a19a7834dca3b786
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