From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcgnT-0006J2-C0 for qemu-devel@nongnu.org; Sun, 25 Nov 2012 13:19:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TcgnR-0000rv-OH for qemu-devel@nongnu.org; Sun, 25 Nov 2012 13:19:15 -0500 Received: from cantor2.suse.de ([195.135.220.15]:38707 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcgnR-0000rj-EX for qemu-devel@nongnu.org; Sun, 25 Nov 2012 13:19:13 -0500 Message-ID: <50B2611C.6010409@suse.de> Date: Sun, 25 Nov 2012 19:19:08 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1353766021-7843-1-git-send-email-aurelien@aurel32.net> In-Reply-To: <1353766021-7843-1-git-send-email-aurelien@aurel32.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH for 1.3] target-i386: enable SSSE3 TCG support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: Igor Mammedov , qemu-devel@nongnu.org, Eduardo Habkost Am 24.11.2012 15:07, schrieb Aurelien Jarno: > SSSE3 support has been added to TCG more than 4 years ago in commit > 4242b1bd8acc19aaaacffdaad4ac23213d72a72b. It has been disabled by > mistake in commit 551a2dec8fa55006a68393b9d6fb63577d2b3f1c. >=20 > Signed-off-by: Aurelien Jarno Reviewed-by: Andreas F=E4rber Looks okay for 1.3 to me. CC'ing some more people who work on the CPU, so that the bit does not get lost again during our refactorings. Aur=E9lien: I have one more patch for x86 CPU in my queue for 1.3 (Haswell), would you be willing to apply both once acked, or should I queue yours for a combined PULL? Andreas > --- > target-i386/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > SSE4.1 and SSE4.2 are wrongly disabled too, but some instructions from > SSE4.2 (I haven't investigated more yet) are wrongly emulated, which > causes some crashes now that GLIBC is using them through gnu indirect > functions. >=20 > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 64c3491..68f6f5d 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -315,7 +315,7 @@ typedef struct x86_def_t { > /* missing: > CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PB= E */ > #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ > - CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ > + CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ > CPUID_EXT_HYPERVISOR) > /* missing: > CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_= EST, --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg