From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Subject: Re: [Qemu-devel] [PATCH V4] target-i386: Enabling IA32_TSC_ADJUST for Qemu KVM guest VMs Date: Tue, 27 Nov 2012 05:05:26 +0100 Message-ID: <50B43C06.3090602@suse.de> References: <1353983386.12838.1.camel@WillAuldHomeLinux> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Will Auld , qemu-devel , Gleb , "mtosatti@redhat.com" , "kvm@vger.kernel.org" , "donald.d.dugger@intel.com" , "jinsong.liu@intel.com" , "xiantao.zhang@intel.com" , "avi@redhat.com" To: will.auld@intel.com Return-path: Received: from cantor2.suse.de ([195.135.220.15]:55372 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933156Ab2K0EFe (ORCPT ); Mon, 26 Nov 2012 23:05:34 -0500 In-Reply-To: <1353983386.12838.1.camel@WillAuldHomeLinux> Sender: kvm-owner@vger.kernel.org List-ID: Am 27.11.2012 03:29, schrieb Will Auld: > CPUID.7.0.EBX[1]=3D1 indicates IA32_TSC_ADJUST MSR 0x3b is supported >=20 > Basic design is to emulate the MSR by allowing reads and writes to th= e > hypervisor vcpu specific locations to store the value of the emulated= MSRs. > In this way the IA32_TSC_ADJUST value will be included in all reads t= o > the TSC MSR whether through rdmsr or rdtsc. >=20 > As this is a new MSR that the guest may access and modify its value n= eeds > to be migrated along with the other MRSs. The changes here are specif= ically > for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code add= ed > for migrating its value. >=20 > Signed-off-by: Will Auld Better, but problems remain (not sure about line endings, didn't check before). It seems the tabs got more rather than getting replaced with four spaces. (And QEMU regressed to Qemu.) =46or future patches you may find the following helpful to detect forma= l errors early yourself (git commit --no-verify overrides): http://blog.vmsplice.net/2011/03/how-to-automatically-run-checkpatchpl.= html Regards, Andreas $ scripts/checkpatch.pl ../wauld_tsc_adjust_v4.eml ERROR: DOS line endings #129: FILE: target-i386/cpu.h:287: +#define MSR_TSC_ADJUST^I^I^I0x0000003b^M$ ERROR: code indent should never use tabs #129: FILE: target-i386/cpu.h:287: +#define MSR_TSC_ADJUST^I^I^I0x0000003b^M$ ERROR: DOS line endings [...] ERROR: code indent should never use tabs #157: FILE: target-i386/kvm.c:645: +^I^Iif (kvm_msr_list->indices[i] =3D=3D MSR_TSC_ADJUST) {^M$ ERROR: DOS line endings #158: FILE: target-i386/kvm.c:646: +^I^I has_msr_tsc_adjust =3D true;^M$ ERROR: code indent should never use tabs #158: FILE: target-i386/kvm.c:646: +^I^I has_msr_tsc_adjust =3D true;^M$ [...] total: 48 errors, 0 warnings, 91 lines checked =2E./wauld_tsc_adjust_v4.eml has style problems, please review. [...] --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3= =BCrnberg From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47295) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdCQS-0007Ym-7H for qemu-devel@nongnu.org; Mon, 26 Nov 2012 23:05:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TdCQQ-0006Ji-QJ for qemu-devel@nongnu.org; Mon, 26 Nov 2012 23:05:36 -0500 Received: from cantor2.suse.de ([195.135.220.15]:55369 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdCQQ-0006H6-GJ for qemu-devel@nongnu.org; Mon, 26 Nov 2012 23:05:34 -0500 Message-ID: <50B43C06.3090602@suse.de> Date: Tue, 27 Nov 2012 05:05:26 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1353983386.12838.1.camel@WillAuldHomeLinux> In-Reply-To: <1353983386.12838.1.camel@WillAuldHomeLinux> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH V4] target-i386: Enabling IA32_TSC_ADJUST for Qemu KVM guest VMs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: will.auld@intel.com Cc: "jinsong.liu@intel.com" , "kvm@vger.kernel.org" , Gleb , "mtosatti@redhat.com" , Will Auld , qemu-devel , "donald.d.dugger@intel.com" , "avi@redhat.com" Am 27.11.2012 03:29, schrieb Will Auld: > CPUID.7.0.EBX[1]=3D1 indicates IA32_TSC_ADJUST MSR 0x3b is supported >=20 > Basic design is to emulate the MSR by allowing reads and writes to the > hypervisor vcpu specific locations to store the value of the emulated M= SRs. > In this way the IA32_TSC_ADJUST value will be included in all reads to > the TSC MSR whether through rdmsr or rdtsc. >=20 > As this is a new MSR that the guest may access and modify its value nee= ds > to be migrated along with the other MRSs. The changes here are specific= ally > for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added > for migrating its value. >=20 > Signed-off-by: Will Auld Better, but problems remain (not sure about line endings, didn't check before). It seems the tabs got more rather than getting replaced with four spaces. (And QEMU regressed to Qemu.) For future patches you may find the following helpful to detect formal errors early yourself (git commit --no-verify overrides): http://blog.vmsplice.net/2011/03/how-to-automatically-run-checkpatchpl.ht= ml Regards, Andreas $ scripts/checkpatch.pl ../wauld_tsc_adjust_v4.eml ERROR: DOS line endings #129: FILE: target-i386/cpu.h:287: +#define MSR_TSC_ADJUST^I^I^I0x0000003b^M$ ERROR: code indent should never use tabs #129: FILE: target-i386/cpu.h:287: +#define MSR_TSC_ADJUST^I^I^I0x0000003b^M$ ERROR: DOS line endings [...] ERROR: code indent should never use tabs #157: FILE: target-i386/kvm.c:645: +^I^Iif (kvm_msr_list->indices[i] =3D=3D MSR_TSC_ADJUST) {^M$ ERROR: DOS line endings #158: FILE: target-i386/kvm.c:646: +^I^I has_msr_tsc_adjust =3D true;^M$ ERROR: code indent should never use tabs #158: FILE: target-i386/kvm.c:646: +^I^I has_msr_tsc_adjust =3D true;^M$ [...] total: 48 errors, 0 warnings, 91 lines checked ../wauld_tsc_adjust_v4.eml has style problems, please review. [...] --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg