From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?VGVyamUgQmVyZ3N0csO2bQ==?= Subject: Re: [RFC v2 8/8] drm: tegra: Add gr2d device Date: Thu, 29 Nov 2012 10:17:44 +0200 Message-ID: <50B71A28.5060807@nvidia.com> References: <1353935954-13763-1-git-send-email-tbergstrom@nvidia.com> <1353935954-13763-9-git-send-email-tbergstrom@nvidia.com> <50B46336.8030605@nvidia.com> <50B476E1.4070403@nvidia.com> <50B47DA8.60609@nvidia.com> <1354011776.1479.31.camel@tellur> <20121127103739.GA3329@avionic-0098.adnet.avionic-design.de> <50B4A483.8030305@nvidia.com> <50B60EFF.1050703@nvidia.com> <1354109602.1479.66.camel@tellur> <50B61845.6060102@nvidia.com> <1354111565.1479.73.camel@tellur> <50B6237B.8010808@nvidia.com> <1354115609.1479.91.camel@tellur> <50B63A70.8020107@nvidia.com> <1354128408.1479.137.camel@tellur> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1354128408.1479.137.camel@tellur> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Lucas Stach Cc: "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linux-tegra@vger.kernel.org" , Arto Merilainen List-Id: linux-tegra@vger.kernel.org T24gMjguMTEuMjAxMiAyMDo0NiwgTHVjYXMgU3RhY2ggd3JvdGU6Cj4gQW0gTWl0dHdvY2gsIGRl biAyOC4xMS4yMDEyLCAxODoyMyArMDIwMCBzY2hyaWViIFRlcmplIEJlcmdzdHLDtm06Cj4+IFNv cnJ5LiBJIHByb21pc2VkIGluIGFub3RoZXIgdGhyZWFkIGEgd3JpdGUtdXAgZXhwbGFpbmluZyB0 aGUgZGVzaWduLiBJCj4+IHN0aWxsIG93ZSB5b3UgZ3V5cyB0aGF0Lgo+IFRoYXQgd291bGQgYmUg cmVhbGx5IG5pY2UgdG8gaGF2ZS4gSSdtIGFsc28gcGFydGljdWxhcmx5IGludGVyZXN0ZWQgaW4K PiBob3cgeW91IHBsYW4gdG8gZG8gc3luY2hyb25pemF0aW9uIG9mIGNvbW1hbmQgc3RyZWFtcyB0 byBkaWZmZXJlbnQKPiBlbmdpbmVzIHdvcmtpbmcgdG9nZXRoZXIsIGlmIHRoYXQncyBub3QgdG9v IG11Y2ggdG8gYXNrIGZvciBub3cuIExpa2UKPiB1c2Vyc3BhY2UgdXBsb2FkaW5nIGEgdGV4dHVy ZSBpbiBhIGJ1ZmZlciwgMkQgZW5naW5lIGRvaW5nIG1pcG1hcAo+IGdlbmVyYXRpb24sIDNEIGVu Z2luZSB1c2luZyBtaXBtYXBwZWQgdGV4dHVyZS4KCkkgY2FuIGJyaWVmbHkgZXhwbGFpbiAoYW5k IHRoZW4gY29weS1wYXN0ZSB0byBhIGNvaGVyZW50IHRleHQgb25jZSBJIGdldAp0byBpdCkgaG93 IGludGVyLWVuZ2luZSBzeW5jaHJvbml6YXRpb24gaXMgZG9uZS4gSXQncyBub3Qgc3BlY2lmaWNh bGx5CmZvciAyRCBvciAzRCwgYnV0IGdlbmVyaWMgdG8gYW55IGhvc3QxeCBjbGllbnQuCgpTeW5j IHBvaW50IHJlZ2lzdGVyIGlzIGEgY291bnRlciB0aGF0IGNhbiBvbmx5IGluY3JlYXNlLiBJdCBz dGFydHMgZnJvbQowIGFuZCBpcyBpbmNyZW1lbnRlZCBieSBhIGhvc3QxeCBjbGllbnQgb3IgQ1BV LiBob3N0MXggY2FuIGZyZWV6ZSBhCmNoYW5uZWwgdW50aWwgYSBzeW5jIHBvaW50IHZhbHVlIGlz IHJlYWNoZWQsIGFuZCBpdCBjYW4gdHJpZ2dlciBhbgppbnRlcnJ1cHQgdXBvbiByZWFjaGluZyBh IHRocmVzaG9sZC4gT24gVGVncmEyIGFuZCBUZWdyYTMgd2UgaGF2ZSAzMgpzeW5jIHBvaW50cy4K Cmhvc3QxeCBjbGllbnRzIGFsbCBpbXBsZW1lbnQgYSBtZXRob2QgZm9yIGluY3JlbWVudGluZyBh IHN5bmMgcG9pbnQKYmFzZWQgb24gYSBjb25kaXRpb24sIGFuZCBvbiBhbGwgb2YgdGhlbSAod2Vs bCwgbm90IGVudGlyZWx5IHRydWUpIHRoZQpyZWdpc3RlciBpcyBudW1iZXIgMC4gVGhlIG1vc3Qg dXNlZCBjb25kaXRpb24gaXMgb3BfZG9uZSwgdGVsbGluZyB0aGUKY2xpZW50IHRvIGluY3JlbWVu dCBzeW5jIHBvaW50IG9uY2UgdGhlIHByZXZpb3VzIG9wZXJhdGlvbnMgYXJlIGRvbmUuCgpJbiBr ZXJuZWwsIHdlIGtlZXAgdHJhY2sgb2YgdGhlIGFjdGl2ZSByYW5nZSBvZiBzeW5jIHBvaW50IHZh bHVlcywgaS5lLgpvbmVzIHdlIGV4cGVjdCB0byBiZSByZWFjaGVkIHdpdGggdGhlIGFjdGl2ZSBq b2JzLiBBY3RpdmUgcmFuZ2UncwptaW5pbXVtIGlzIHRoZSBjdXJyZW50IHZhbHVlIHJlYWQgZnJv bSBodyBhbmQgc2hhZG93ZWQgaW4gbWVtb3J5LiBBdCBqb2IKc3VibWl0IHRpbWUsIGtlcm5lbCBp bmNyZW1lbnRzIHRoZSBtYXhpbXVtIGJ5IHRoZSBudW1iZXIgb2Ygc3luYyBwb2ludHMKdGhlIHN0 cmVhbSBhbm5vdW5jZXMgaXQgd2lsbCBwZXJmb3JtLiBBZnRlciBwZXJmb3JtaW5nIHRoZSBpbmNy ZW1lbnQsIHdlCmhhdmUgYSBudW1iZXIsIHdoaWNoIHRoZSBzeW5jIHBvaW50IGlzIHN1cHBvc2Vk IHRvIHJlYWNoIGF0IHRoZSBlbmQgb2YKc3VibWl0LiBUaGF0IG51bWJlciBpcyB0aGUgdGhlIGZl bmNlIGFuZCBpdCBpcyByZWNvcmRlZCBpbiBrZXJuZWwgYW5kCnJldHVybmVkIHRvIHVzZXIgc3Bh Y2UuCgpTbywgd2hlbiB1c2VyIHNwYWNlIGZsdXNoZXMsIGl0IHJlY2VpdmVzIGEgZmVuY2UuIEl0 IGNhbiBpbnNlcnQgdGhlCmZlbmNlIGludG8gYW5vdGhlciBjb21tYW5kIHN0cmVhbSBhcyBwYXJh bWV0ZXIgdG8gYSBob3N0MXggY2hhbm5lbCB3YWl0LgpUaGlzIG1ha2VzIHRoYXQgY2hhbm5lbCBm cmVlemUgdW50aWwgYW4gb3BlcmF0aW9uIGluIGFub3RoZXIgY2hhbm5lbCBpcwpmaW5pc2hlZC4g VGhhdCdzIGhvdyBkaWZmZXJlbnQgaG9zdDF4IGNsaWVudHMgY2FuIHN5bmNocm9uaXplIHdpdGhv dXQKdXNpbmcgQ1BVLgoKS2VybmVsJ3Mgc3luYyBwb2ludCB3YWl0IGVzc2VudGlhbGx5IHB1dHMg dGhlIHByb2Nlc3MgaW50byBzbGVlcCB1bnRpbApob3N0MXggc2VuZHMgYW4gaW50ZXJydXB0IGFu ZCB3ZSBkZXRlcm1pbmUgdGhlIHZhbHVlIHRoYXQgYSBwcm9jZXNzIGlzCndhaXRpbmcgZm9yLCBo YXMgYmVlbiByZWFjaGVkLgoKT24gdG9wIG9mIHRoaXMsIHdlIGd1YXJkIGFnYWluc3Qgd3JhcHBp bmcgaXNzdWVzIGJ5IG51bGxpbmcgb3V0IGFueSBzeW5jCnBvaW50IHdhaXRzIChDUFUgb3IgaW5z aWRlIHN0cmVhbSkgdGhhdCBhcmUgd2FpdGluZyBmb3IgdmFsdWVzIG91dHNpZGUKdGhlIGFjdGl2 ZSByYW5nZSwgYW5kIHdlIGhhdmUgYSB0aW1lb3V0IGZvciBqb2JzIHNvIHRoYXQgd2UgY2FuIGtp Y2sgb3V0Cm1pc2JlaGF2aW5nIGNvbW1hbmQgc3RyZWFtcy4KCj4gQWggeWVzIEkgc2VlLiBTbyBp ZiB3ZSBjb25zaWRlciBudmhvc3QgdG8gYmUgdGhlIGNlbnRyYWwgZW50aXR5IGluCj4gY2hhcmdl IG9mIGNvbnRyb2xsaW5nIGFsbCBob3N0MXggY2xpZW50cyBhbmQgdGVncmFkcm0gYXMgdGhlIGlu dGVyZmFjZQo+IHRoYXQgaGFwcGVucyB0byBidW5kbGUgZGlzcGxheSwgMmQgYW5kIDNkIGVuZ2lu ZSBmdW5jdGlvbmFsaXR5IGludG8gaXQncwo+IGludGVyZmFjZSB3ZSBzaG91bGQgcHJvYmFibHkg YWltIGZvciB0d28gdGhpbmdzOgo+IDEuIE1vdmUgZXZlcnl0aGluZyBuZWVkZWQgYnkgYWxsIGVu Z2luZXMgZG93biBpbnRvIG52aG9zdCAoSSBlc3BlY2lhbGx5Cj4gc2VlIHRoZSBhbGxvY2F0b3Ig ZmFsbGluZyB1bmRlciB0aGlzIHBvaW50LCBJJ2xsIGV4cGxhaW4gd2h5IHRoaXMgd291bGQKPiBi ZSBiZW5lZmljaWFsIGEgYml0IGxhdGVyKQoKT2suIFRoaXMgaXMgYWxtb3N0IHRoZSBjdXJyZW50 IGRlc2lnbiwgZXhjZXB0IGZvciB0aGUgYWxsb2NhdG9yLgoKPiAyLiBNb3ZlIHRoZSBleHBvc2Vk IERSTSBpbnRlcmZhY2UgbW9yZSBpbiBsaW5lIHdpdGggb3RoZXIgRFJNIGRyaXZlcnMuCj4gUGxl YXNlIHRha2UgYSBsb29rIGF0IGhvdyBmb3IgZXhhbXBsZSB0aGUgR0VNX0VYRUNCVUYgaW9jdGwg d29ya3Mgb24KPiBvdGhlciBkcml2ZXJzIHRvIGdldCBhIGZlZWxpbmcgb2Ygd2hhdCBJJ20gdGFs a2luZyBhYm91dC4gRXZlcnl0aGluZwo+IHVzaW5nIHRoZSBkaXNwbGF5LCAyRCBhbmQgbWF5YmUg bGF0ZXIgb24gdGhlIDNEIGVuZ2luZSBzaG91bGQgb25seSBkZWFsCj4gd2l0aCBHRU0gaGFuZGxl cy4gSSByZWFsbHkgZG9uJ3QgbGlrZSB0aGUgaWRlYSBvZiBoYXZpbmcgYSBzaW5nbGUKPiB1c2Vy c3BhY2UgYXBwbGljYXRpb24sIHdoaWNoIHVzZXMgZW5naW5lcyB3aXRoIHNpbWlsYXIgYW5kIGtu b3duCj4gcmVxdWlyZW1lbnRzIChERFgpIGRlYWxpbmcgd2l0aCBkbWEtYnVmIGhhbmRsZXMgb3Ig b3RoZXIgc2ltaWxhciBoaWdoCj4gb3ZlcmhlYWQgc3R1ZmYgdG8gZG8gdGhlIG1vc3QgYmFzaWMg dGFza3MuCj4gSWYgd2UgbW92ZSBkb3duIHRoZSBhbGxvY2F0b3IgaW50byBudmhvc3Qgd2UgY2Fu IHVzZSBidWZmZXJzIGFsbG9jYXRlZAo+IGZyb20gdGhpcyB0byBiYWNrIEdFTSBvciBWNEwyIGJ1 ZmZlcnMgdHJhbnNwYXJlbnRseS4gVGhlIGlvY3RsIHRvCj4gYWxsb2NhdGUgYSBHRU0gYnVmZmVy IHNob3VsZG4ndCBkbyBtdWNoIG1vcmUgdGhhbiB3cmFwcGluZyB0aGUgbnZob3N0Cj4gYnVmZmVy LgoKT2ssIHRoaXMgaXMgYWN0dWFsbHkgd2hhdCB3ZSBkbyBkb3duc3RyZWFtLiBXZSB1c2UgZG1h LWJ1ZiBoYW5kbGVzIG9ubHkKZm9yIHB1cnBvc2VzIHdoZXJlIHRoZXkncmUgcmVhbGx5IG5lZWRl ZCAoaW4gZmFjdCwgbm9uZSB5ZXQpLCBhbmQgdXNlCm91ciBkb3duc3RyZWFtIGFsbG9jYXRvciBo YW5kbGVzIGZvciB0aGUgcmVzdC4gSSBkaWQgdGhpcywgYmVjYXVzZQpiZW5jaG1hcmtzIHdlcmUg c2hvd2luZyB0aGF0IG1lbW9yeSBtYW5hZ2VtZW50IG92ZXJoZWFkIHNob290IHRocm91Z2gKdGhl IHJvb2YgaWYgSSB0cmllZCBkb2luZyBldmVyeXRoaW5nIHZpYSBkbWEtYnVmLgoKV2UgY2FuIG1v dmUgc3VwcG9ydCBmb3IgYWxsb2NhdGluZyBHRU0gaGFuZGxlcyB0byBudmhvc3QsIGFuZCBHRU0K aGFuZGxlcyBjYW4gYmUgdHJlYXRlZCBqdXN0IGFzIGFub3RoZXIgbWVtb3J5IGhhbmRsZSB0eXBl IGluIG52aG9zdC4KdGVncmFkcm0gd291bGQgdGhlbiBjYWxsIG52aG9zdCBmb3IgYWxsb2NhdGlv bi4KCgo+IFRoaXMgbWF5IGFsc28gc29sdmUgeW91ciBwcm9ibGVtIHdpdGggaGF2aW5nIG11bHRp cGxlIG1hcHBpbmdzIG9mIHRoZQo+IHNhbWUgYnVmZmVyIGludG8gdGhlIHZlcnkgc2FtZSBhZGRy ZXNzIHNwYWNlLCBhcyBudmhvc3QgaXMgdGhlIHNpbmdsZQo+IGluc3RhbmNlIHRoYXQgbWFuYWdl cyBhbGwgaG9zdDF4IGNsaWVudCBhZGRyZXNzIHNwYWNlcy4gSWYgdGhlIGJ1ZmZlciBpcwo+IG9y aWdpbmF0aW5nIGZyb20gdGhlcmUgeW91IGNhbiBlYXNpbHkgY2hlY2sgaWYgaXQncyBhbHJlYWR5 IG1hcHBlZC4gRm9yCj4gVGVncmEgMyB0byBkbyB0aGluZ3MgaW4gYW4gZWZmaWNpZW50IHdheSB3 ZSBsaWtlbHkgaGF2ZSB0byBtb3ZlIGF3YXkKPiBmcm9tIGRlYWxpbmcgd2l0aCB0aGUgRE1BIEFQ SSB0byBkZWFsaW5nIHdpdGggdGhlIElPTU1VIEFQSSwgdGhpcyBnZXRzIGEKPiBfbG90XyBlYXNp ZXJfIGlmIHlvdSBoYXZlIGEgc2luZ2xlIHBvaW50IHdoZXJlIHlvdSBtYW5hZ2UgbWVtb3J5Cj4g YWxsb2NhdGlvbiBhbmQgYWRkcmVzcyBzcGFjZS4KClllcCwgdGhpcyB3b3VsZCBkZWZpbml0ZWx5 IHNpbXBsaWZ5IG91ciBJT01NVSBwcm9ibGVtLiBCdXQsIEkgdGhvdWdodAp0aGUgY2Fub25pY2Fs IHdheSBvZiBkZWFsaW5nIHdpdGggZGV2aWNlIG1lbW9yeSBpcyBETUEgQVBJLCBhbmQgeW91J3Jl CnNheWluZyB0aGF0IHdlIHNob3VsZCBqdXN0IGJ5cGFzcyBpdCBhbmQgY2FsbCBJT01NVSBkaXJl Y3RseT8KCj4+IENvbmN1cnJlbmN5IGlzIGhhbmRsZWQgd2l0aCBzeW5jIHBvaW50cy4gVXNlciBz cGFjZSB3aWxsIGtub3cgd2hlbiBhCj4+IGNvbW1hbmQgc3RyZWFtIGlzIHByb2Nlc3NlZCBhbmQg Y2FuIGJlIHJldXNlZCBieSBjb21wYXJpbmcgdGhlIGN1cnJlbnQKPj4gc3luYyBwb2ludCB2YWx1 ZSwgYW5kIHRoZSBmZW5jZSB0aGF0IDJEIGRyaXZlciByZXR1cm5lZCB0byB1c2VyIHNwYWNlLgo+ PiBVc2VyIHNwYWNlIGNhbiBoYXZlIGEgcG9vbCBvZiBidWZmZXJzIGFuZCBjYW4gcmVjeWNsZSB3 aGVuIGl0IGtub3dzIGl0Cj4+IGNhbiBkbyBzby4gQnV0LCB0aGlzIGlzIG5vdCBlbmZvcmNlZCBi eSBrZXJuZWwuCj4+Cj4gVGhpcyBpcyB0aGUgcG9pbnQgd2hlcmUgd2UgaGF2ZSBkaWZmZXI6IFlv dSBoYXZlIHRvIGRlYWwgd2l0aCBzeW5jcHRzIGluCj4ga2VybmVsIGFueXdheSwgb3RoZXJ3aXNl IHlvdSBkb24ndCBrbm93IHdoZW4gaXQncyBzYWZlIHRvIGRlc3Ryb3kgYQo+IGJ1ZmZlci4gQW5k IG5vLCB1c2Vyc3BhY2Ugc2hvdWxkIG5vdCBoYXZlIHRoZSBhYmlsaXR5IHRvIGRlc3Ryb3kgYQo+ IGJ1ZmZlciBpdHNlbGYsIHVzZXJzcGFjZSBzaG91bGQgYWx3YXlzIGp1c3QgYmUgYWJsZSB0byBm cmVlIGl0J3MKPiByZWZlcmVuY2UgdG8gdGhlIGJ1ZmZlci4gUmVtZW1iZXI6IG5ldmVyIHRydXN0 IHRoZSB1c2Vyc3BhY2UuIEFuZCBpZiB5b3UKPiBhcmUgZGVhbGluZyB3aXRoIHN5bmNwdHMgaW4g a2VybmVsIGFueXdheSwgeW91IGNhbiBqdXN0IGdvIGFoZWFkIGFuZAo+IGVuZm9yY2Ugc29tZSBz YW5lIGNvbmN1cnJlbmN5IHJ1bGVzLiBUaGVyZSBtYXkgYmUgc29tZSBjb3JlbmVyIGNhc2VzCj4g cmVsYXRlZCB0byB1c2Vyc3BhY2Ugc3ViYWxsb2NhdGluZyBhIGtlcm5lbCBidWZmZXIsIHdoaWNo IG1pZ2h0IG5lZWQKPiBzb21lIG1vcmUgdGhvdWdodCBzdGlsbCwgYnV0IHRoYXQncyBub3QgYSB2 YWxpZCBleGN1c2UgdG8gbm90IGRvIGFueQo+IGNvbmN1cnJlbmN5IHZhbGlkYXRpb24gaW4ga2Vy bmVsLgoKbnZob3N0IGlzIGFscmVhZHkgZGVhbGluZyB3aXRoIHN5bmMgcG9pbnRzLCBhbmQgcHJv dGVjdGluZyBtZW1vcnkgZnJvbQpiZWluZyBmcmVlZCBpZiBpdCdzIHVzZWQuIFdlIHVzZSByZWZj b3VudGluZyB0byBkbyB0aGF0LiBXaGVuIGEgam9iIGlzCnNlbnQgdG8gaHcsIHdlIGdldCByZWZl cmVuY2UgdG8gYWxsIG1lbW9yeSAoY29tbWFuZCBzdHJlYW0gJiBzdXJmYWNlcykuCldoZW4gam9i IGlzIGRvbmUgKGZlbmNlIHJlYWNoZWQpLCBudmhvc3QgdW5yZWZlcmVuY2VzIHRoZW0uIFVzZXIg c3BhY2UKY2FuIGZyZWUgdGhlIG1lbW9yeSBpdCBoYXMgYWxsb2NhdGVkLCBidXQga2VybmVsIHdv dWxkIGhvbGQgb24gdG8gaXQKdW50aWwgaXQncyBzYWZlIHRvIGFjdHVhbGx5IHJlbGVhc2UgdGhl IG1lbW9yeS4KCj4+IFRoZSBkaWZmZXJlbmNlIHdpdGggeW91ciBwcm9wb3NhbCBhbmQgd2hhdCBJ IHBvc3RlZCBpcyB0aGUgbGV2ZWwgb2YKPj4gY29udHJvbCB1c2VyIHNwYWNlIGhhcyBvdmVyIGl0 cyBjb21tYW5kIHN0cmVhbSBtYW5hZ2VtZW50LiBCdXQgYXMgc2FpZCwKPj4gMkQgc3RyZWFtcyBh cmUgc28gc2hvcnQgdGhhdCBteSBndWVzcyBpcyB0aGF0IHRoZXJlJ3Mgbm90IHRvbyBtdWNoCj4+ IHBlbmFsdHkgY29weWluZyBpdCB0byBrZXJuZWwgbWFuYWdlZCBob3N0MXggcHVzaCBidWZmZXIg ZGlyZWN0bHkgaW5zdGVhZAo+PiBvZiBpbnNlcnRpbmcgYSBHQVRIRVIgcmVmZXJlbmNlLgo+Pgo+ IFRoaXMgYW4gaW1wbGVtZW50YXRpb24gZGV0YWlsLiBXaGV0aGVyIHlvdSBzaG9vdCBkb3duIHRo ZSBvbGQgcHVzaGJ1Zgo+IG1hcHBpbmcgYW5kIGluc2VydCBhIG5ldyBvbmUgcG9pbnRpbmcgdG8g ZnJlZSBiYWNraW5nIG1lbW9yeSAod2hpY2ggbWF5Cj4gYmUgdGhlIHdheSB0byBnbyBmb3IgM0Qp IG9yIGRvIGFuIGltbWVkaWF0ZSBjb3B5IG9mIHRoZSBjaGFubmVsIHB1c2hidWYKPiBjb250ZW50 cyB0byB0aGUgaG9zdDF4IHB1c2hidWYgKHdoaWNoIG1heSBiZSBiZW5lZmljaWFsIGZvciB2ZXJ5 IHNtYWxsCj4gcHVzaHMpIGlzIGFsbCB0aGUgc2FtZS4gQm90aCBtZXRob2RzIGltcGxpY2l0bHkg Z3VhcmFudGVlIHRoYXQgdGhlCj4gbWVtb3J5IG1hcHBlZCBieSB1c2Vyc3BhY2UgYWx3YXlzIHBv aW50cyB0byBhIGxvY2F0aW9uIHRoZSBDUFUgY2FuIHdyaXRlCj4gdG8gd2l0aG91dCBpbnRlcmZl cmluZyB3aXRoIHRoZSBHUFUuCgpPay4gQmFzZWQgb24gdGhpcywgSSBwcm9wb3NlIHRoZSB3YXkg dG8gZ28gZm9yIGNhc2VzIHdpdGhvdXQgSU9NTVUKc3VwcG9ydCBhbmQgYWxsIFRlZ3JhMjAgY2Fz ZXMgKGFzIFRlZ3JhMjAncyBHQVJUIGNhbid0IHByb3ZpZGUgbWVtb3J5CnByb3RlY3Rpb24pIGlz IHRvIGNvcHkgdGhlIHN0cmVhbSB0byBob3N0MXggcHVzaCBidWZmZXIuIEluIFRlZ3JhMzAgd2l0 aApJT01NVSBzdXBwb3J0IHdlIGNhbiBqdXN0IHJlZmVyZW5jZSB0aGUgYnVmZmVyLiBUaGlzIHdh eSB3ZSBkb24ndCBoYXZlCnRvIGRvIGV4cGVuc2l2ZSBNTVUgb3BlcmF0aW9ucy4KCj4gSSByZWFs bHkgZW5qb3llZCB0aGUgZGlzY3Vzc2lvbiBzbyBmYXIgYW5kIGhvcGUgd2UgY2FuIGdldCB0byB0 aGUgcG9pbnQKPiB3aGVyZSB3ZSBoYXZlIGEgbmljZSBkZXNpZ24vaW50ZXJmYWNlLCB3b3JraW5n IHRvZ2V0aGVyLgoKVGhhbmtzLiBJIGRvbid0IGhhdmUgYSBzdHJpY3QgZGVhZGxpbmUgZm9yIHVw c3RyZWFtaW5nLCBzbyBJJ20gZmluZQpjb250aW51aW5nIHdpdGggZGlzY3Vzc2lvbiB1bnRpbCB3 ZSdyZSBzZXR0bGVkLCBhbmQgdGhlbiBkb2luZyB0aGUKbmVlZGVkIGNoYW5nZXMuCgpNeSBnb2Fs IGlzIHRvIGVuZCB1cCB3aXRoIHNvbWV0aGluZyB0aGF0IHdlIGNhbiB0YWtlIGFkdmFudGFnZSBv ZiBpbgp1cHN0cmVhbSB3aXRoIHRlZ3JhZHJtIGFuZCAyRCwgYnV0IGFsc28gZG93bnN0cmVhbSB3 aXRoIHRoZSByZXN0IG9mIHRoZQpkb3duc3RyZWFtIHN0YWNrLiBUaGF0IHdheSB0aGVyZSdzIG5v IHRlY2huaWNhbCBiYXJyaWVyIHRvIHVzIG1vdmluZyBpbgpkb3duc3RyZWFtIHRvIHVzZSB0aGUg dXBzdHJlYW0gY29kZS4KClRlcmplCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVk ZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8v ZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754358Ab2K2IOF (ORCPT ); Thu, 29 Nov 2012 03:14:05 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:11816 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754305Ab2K2IOB convert rfc822-to-8bit (ORCPT ); Thu, 29 Nov 2012 03:14:01 -0500 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Thu, 29 Nov 2012 00:13:53 -0800 Message-ID: <50B71A28.5060807@nvidia.com> Date: Thu, 29 Nov 2012 10:17:44 +0200 From: =?UTF-8?B?VGVyamUgQmVyZ3N0csO2bQ==?= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: Lucas Stach CC: Dave Airlie , Thierry Reding , "linux-tegra@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , Arto Merilainen Subject: Re: [RFC v2 8/8] drm: tegra: Add gr2d device References: <1353935954-13763-1-git-send-email-tbergstrom@nvidia.com> <1353935954-13763-9-git-send-email-tbergstrom@nvidia.com> <50B46336.8030605@nvidia.com> <50B476E1.4070403@nvidia.com> <50B47DA8.60609@nvidia.com> <1354011776.1479.31.camel@tellur> <20121127103739.GA3329@avionic-0098.adnet.avionic-design.de> <50B4A483.8030305@nvidia.com> <50B60EFF.1050703@nvidia.com> <1354109602.1479.66.camel@tellur> <50B61845.6060102@nvidia.com> <1354111565.1479.73.camel@tellur> <50B6237B.8010808@nvidia.com> <1354115609.1479.91.camel@tellur> <50B63A70.8020107@nvidia.com> <1354128408.1479.137.camel@tellur> In-Reply-To: <1354128408.1479.137.camel@tellur> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28.11.2012 20:46, Lucas Stach wrote: > Am Mittwoch, den 28.11.2012, 18:23 +0200 schrieb Terje Bergström: >> Sorry. I promised in another thread a write-up explaining the design. I >> still owe you guys that. > That would be really nice to have. I'm also particularly interested in > how you plan to do synchronization of command streams to different > engines working together, if that's not too much to ask for now. Like > userspace uploading a texture in a buffer, 2D engine doing mipmap > generation, 3D engine using mipmapped texture. I can briefly explain (and then copy-paste to a coherent text once I get to it) how inter-engine synchronization is done. It's not specifically for 2D or 3D, but generic to any host1x client. Sync point register is a counter that can only increase. It starts from 0 and is incremented by a host1x client or CPU. host1x can freeze a channel until a sync point value is reached, and it can trigger an interrupt upon reaching a threshold. On Tegra2 and Tegra3 we have 32 sync points. host1x clients all implement a method for incrementing a sync point based on a condition, and on all of them (well, not entirely true) the register is number 0. The most used condition is op_done, telling the client to increment sync point once the previous operations are done. In kernel, we keep track of the active range of sync point values, i.e. ones we expect to be reached with the active jobs. Active range's minimum is the current value read from hw and shadowed in memory. At job submit time, kernel increments the maximum by the number of sync points the stream announces it will perform. After performing the increment, we have a number, which the sync point is supposed to reach at the end of submit. That number is the the fence and it is recorded in kernel and returned to user space. So, when user space flushes, it receives a fence. It can insert the fence into another command stream as parameter to a host1x channel wait. This makes that channel freeze until an operation in another channel is finished. That's how different host1x clients can synchronize without using CPU. Kernel's sync point wait essentially puts the process into sleep until host1x sends an interrupt and we determine the value that a process is waiting for, has been reached. On top of this, we guard against wrapping issues by nulling out any sync point waits (CPU or inside stream) that are waiting for values outside the active range, and we have a timeout for jobs so that we can kick out misbehaving command streams. > Ah yes I see. So if we consider nvhost to be the central entity in > charge of controlling all host1x clients and tegradrm as the interface > that happens to bundle display, 2d and 3d engine functionality into it's > interface we should probably aim for two things: > 1. Move everything needed by all engines down into nvhost (I especially > see the allocator falling under this point, I'll explain why this would > be beneficial a bit later) Ok. This is almost the current design, except for the allocator. > 2. Move the exposed DRM interface more in line with other DRM drivers. > Please take a look at how for example the GEM_EXECBUF ioctl works on > other drivers to get a feeling of what I'm talking about. Everything > using the display, 2D and maybe later on the 3D engine should only deal > with GEM handles. I really don't like the idea of having a single > userspace application, which uses engines with similar and known > requirements (DDX) dealing with dma-buf handles or other similar high > overhead stuff to do the most basic tasks. > If we move down the allocator into nvhost we can use buffers allocated > from this to back GEM or V4L2 buffers transparently. The ioctl to > allocate a GEM buffer shouldn't do much more than wrapping the nvhost > buffer. Ok, this is actually what we do downstream. We use dma-buf handles only for purposes where they're really needed (in fact, none yet), and use our downstream allocator handles for the rest. I did this, because benchmarks were showing that memory management overhead shoot through the roof if I tried doing everything via dma-buf. We can move support for allocating GEM handles to nvhost, and GEM handles can be treated just as another memory handle type in nvhost. tegradrm would then call nvhost for allocation. > This may also solve your problem with having multiple mappings of the > same buffer into the very same address space, as nvhost is the single > instance that manages all host1x client address spaces. If the buffer is > originating from there you can easily check if it's already mapped. For > Tegra 3 to do things in an efficient way we likely have to move away > from dealing with the DMA API to dealing with the IOMMU API, this gets a > _lot_ easier_ if you have a single point where you manage memory > allocation and address space. Yep, this would definitely simplify our IOMMU problem. But, I thought the canonical way of dealing with device memory is DMA API, and you're saying that we should just bypass it and call IOMMU directly? >> Concurrency is handled with sync points. User space will know when a >> command stream is processed and can be reused by comparing the current >> sync point value, and the fence that 2D driver returned to user space. >> User space can have a pool of buffers and can recycle when it knows it >> can do so. But, this is not enforced by kernel. >> > This is the point where we have differ: You have to deal with syncpts in > kernel anyway, otherwise you don't know when it's safe to destroy a > buffer. And no, userspace should not have the ability to destroy a > buffer itself, userspace should always just be able to free it's > reference to the buffer. Remember: never trust the userspace. And if you > are dealing with syncpts in kernel anyway, you can just go ahead and > enforce some sane concurrency rules. There may be some corener cases > related to userspace suballocating a kernel buffer, which might need > some more thought still, but that's not a valid excuse to not do any > concurrency validation in kernel. nvhost is already dealing with sync points, and protecting memory from being freed if it's used. We use refcounting to do that. When a job is sent to hw, we get reference to all memory (command stream & surfaces). When job is done (fence reached), nvhost unreferences them. User space can free the memory it has allocated, but kernel would hold on to it until it's safe to actually release the memory. >> The difference with your proposal and what I posted is the level of >> control user space has over its command stream management. But as said, >> 2D streams are so short that my guess is that there's not too much >> penalty copying it to kernel managed host1x push buffer directly instead >> of inserting a GATHER reference. >> > This an implementation detail. Whether you shoot down the old pushbuf > mapping and insert a new one pointing to free backing memory (which may > be the way to go for 3D) or do an immediate copy of the channel pushbuf > contents to the host1x pushbuf (which may be beneficial for very small > pushs) is all the same. Both methods implicitly guarantee that the > memory mapped by userspace always points to a location the CPU can write > to without interfering with the GPU. Ok. Based on this, I propose the way to go for cases without IOMMU support and all Tegra20 cases (as Tegra20's GART can't provide memory protection) is to copy the stream to host1x push buffer. In Tegra30 with IOMMU support we can just reference the buffer. This way we don't have to do expensive MMU operations. > I really enjoyed the discussion so far and hope we can get to the point > where we have a nice design/interface, working together. Thanks. I don't have a strict deadline for upstreaming, so I'm fine continuing with discussion until we're settled, and then doing the needed changes. My goal is to end up with something that we can take advantage of in upstream with tegradrm and 2D, but also downstream with the rest of the downstream stack. That way there's no technical barrier to us moving in downstream to use the upstream code. Terje