From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adam Jackson Subject: Re: [PATCH 3/3] drm/i915: fix FDI lane calculation Date: Thu, 29 Nov 2012 11:16:04 -0500 Message-ID: <50B78A44.6090109@redhat.com> References: <1354195773-4022-1-git-send-email-przanoni@gmail.com> <1354195773-4022-3-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C870E6610 for ; Thu, 29 Nov 2012 08:16:12 -0800 (PST) In-Reply-To: <1354195773-4022-3-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On 11/29/12 8:29 AM, Paulo Zanoni wrote: > From: Paulo Zanoni > > The previous code was making the bps value 5% higher than what the > spec says, which was enough to make certain VGA modes require 3 lanes > instead of 2, which makes us reject these modes on Haswell since it > only has 2 FDI lanes. For previous gens this was not much of a > problem, since they had 4 lanes, and requiring more lanes than the > needed is ok, as long as you have all the lanes. > > Notice that this might improve the case where we use pipes B and C on > Ivy Bridge since both pipes only have 4 lanes to share (see > ironlake_check_fdi_lanes). Fine with me. I'm not entirely sure the SS check I had there was necessary; I do remember the docs saying to account for it, but I'm not sure the check we had there was correct. Reviewed-by: Adam Jackson - ajax