From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Subject: Re: [Qemu-devel] [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs Date: Fri, 30 Nov 2012 15:35:54 +0100 Message-ID: <50B8C44A.6080404@suse.de> References: <1353994338.31363.15.camel@WillAuldHomeLinux> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Will Auld , qemu-devel , Gleb , "mtosatti@redhat.com" , "kvm@vger.kernel.org" , "donald.d.dugger@intel.com" , "jinsong.liu@intel.com" , "xiantao.zhang@intel.com" , "avi@redhat.com" To: will.auld@intel.com Return-path: Received: from cantor2.suse.de ([195.135.220.15]:45138 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752774Ab2K3Of6 (ORCPT ); Fri, 30 Nov 2012 09:35:58 -0500 In-Reply-To: <1353994338.31363.15.camel@WillAuldHomeLinux> Sender: kvm-owner@vger.kernel.org List-ID: Am 27.11.2012 06:32, schrieb Will Auld: > CPUID.7.0.EBX[1]=3D1 indicates IA32_TSC_ADJUST MSR 0x3b is supported >=20 > Basic design is to emulate the MSR by allowing reads and writes to th= e > hypervisor vcpu specific locations to store the value of the emulated= MSRs. > In this way the IA32_TSC_ADJUST value will be included in all reads t= o > the TSC MSR whether through rdmsr or rdtsc. >=20 > As this is a new MSR that the guest may access and modify its value n= eeds > to be migrated along with the other MRSs. The changes here are specif= ically > for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code add= ed > for migrating its value. >=20 > Signed-off-by: Will Auld Reviewed-by: Andreas F=C3=A4rber from the CPU perspective. Thanks, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3= =BCrnberg From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49586) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TeRhs-0003i0-VJ for qemu-devel@nongnu.org; Fri, 30 Nov 2012 09:36:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TeRhn-0004rq-MT for qemu-devel@nongnu.org; Fri, 30 Nov 2012 09:36:44 -0500 Received: from cantor2.suse.de ([195.135.220.15]:45137 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TeRhn-0004nu-Fz for qemu-devel@nongnu.org; Fri, 30 Nov 2012 09:36:39 -0500 Message-ID: <50B8C44A.6080404@suse.de> Date: Fri, 30 Nov 2012 15:35:54 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1353994338.31363.15.camel@WillAuldHomeLinux> In-Reply-To: <1353994338.31363.15.camel@WillAuldHomeLinux> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: will.auld@intel.com Cc: "jinsong.liu@intel.com" , "kvm@vger.kernel.org" , Gleb , "mtosatti@redhat.com" , Will Auld , qemu-devel , "donald.d.dugger@intel.com" , "avi@redhat.com" Am 27.11.2012 06:32, schrieb Will Auld: > CPUID.7.0.EBX[1]=3D1 indicates IA32_TSC_ADJUST MSR 0x3b is supported >=20 > Basic design is to emulate the MSR by allowing reads and writes to the > hypervisor vcpu specific locations to store the value of the emulated M= SRs. > In this way the IA32_TSC_ADJUST value will be included in all reads to > the TSC MSR whether through rdmsr or rdtsc. >=20 > As this is a new MSR that the guest may access and modify its value nee= ds > to be migrated along with the other MRSs. The changes here are specific= ally > for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added > for migrating its value. >=20 > Signed-off-by: Will Auld Reviewed-by: Andreas F=C3=A4rber from the CPU perspective. Thanks, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg