From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 1/3] apf27: add missing constant to mx27
Date: Fri, 07 Dec 2012 15:01:18 +0100 [thread overview]
Message-ID: <50C1F6AE.8080805@denx.de> (raw)
In-Reply-To: <1354358693-28737-2-git-send-email-tremyfr@yahoo.fr>
On 01/12/2012 11:44, Philippe Reynes wrote:
> Add some missing constant (chip select, ...), and
> a file mxc_nand.h with the NFC constant.
>
> Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> ---
Hi Philippe,
> arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 34 ++++++++++++
> arch/arm/include/asm/arch-mx27/imx-regs.h | 11 ++++-
> arch/arm/include/asm/arch-mx27/mxc_nand.h | 83 +++++++++++++++++++++++++++++
> 3 files changed, 127 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
>
> diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
> index f3a8d7b..b95c58c 100644
> --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
> +++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
> @@ -34,6 +34,7 @@ int main(void)
> DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
> DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
> DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
> + DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
>
> DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
> DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
> @@ -41,5 +42,38 @@ int main(void)
> DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
> DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
>
> + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
> + offsetof(struct system_control_regs, gpcr));
> + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
> + offsetof(struct system_control_regs, fmcr));
> + DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE +
> + offsetof(struct system_control_regs, dscr2));
> + DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE +
> + offsetof(struct system_control_regs, dscr3));
> + DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE +
> + offsetof(struct system_control_regs, dscr7));
> + DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE +
> + offsetof(struct system_control_regs, dscr10));
> +
> + DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
> + DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
> + DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
> + DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
> + DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
> + DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
> + DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
> + DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
> + DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
> + DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
> + DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
> + DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
> + DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
> + DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
> + DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
> + DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
> + DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
> + DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
> + DEFINE(EIM, IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
> +
> return 0;
> }
> diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
> index 2f6c823..d3a14e1 100644
> --- a/arch/arm/include/asm/arch-mx27/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
> @@ -185,7 +185,7 @@ struct iim_regs {
> struct fuse_bank {
> u32 fuse_regs[0x20];
> u32 fuse_rsvd[0xe0];
> - } bank[1];
> + } bank[2];
> };
I think the
>
> struct fuse_bank0_regs {
> @@ -511,4 +511,13 @@ struct fuse_bank0_regs {
> #define IIM_ERR_SNSE (1 << 2)
> #define IIM_ERR_PARITYE (1 << 1)
>
> +/*
> + * Memory areas of the NFC
> + */
> +#define IMX_NFC_BASE (0xD8000000)
> +#define IMX_NFC_MAIN_AREA0 (0xD8000000)
> +#define IMX_NFC_MAIN_AREA1 (0xD8000200)
> +#define IMX_NFC_SPARE_AREA0 (0xD8000800)
> +#define IMX_NFC_REGS (0xD8000E00)
> +
> #endif /* _IMX_REGS_H */
> diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h
> new file mode 100644
> index 0000000..564419e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
> @@ -0,0 +1,83 @@
> +/*
> + * (c) 2012 Philippe Reynes <tremyfr@yahoo.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __MXC_NAND_H
> +#define __MXC_NAND_H
> +
> +/*
> + * NFC registers address offset
> + */
> +#define NFC_OFFSET_BUFSIZE (0x00) /* Internal SRAM Size */
> +#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for
> + Lock Check */
> +#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data
> + Transfer To/From Flash Mem */
> +#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */
> +#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */
> +#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock
> + Control */
> +#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of
> + Flash Operation */
> +#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC Error Position of Main
> + Area Data Error */
> +#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare
> + Area Data Error */
> +#define NFC_OFFSET_WRPROT (0x12) /* Nand Flash Write Protection */
> +#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write
> + Protection Unlock */
> +#define NFC_OFFSET_UNLOCKEND_BLKADDR (0x16) /* End Address for Write
> + Protection Unlock */
> +#define NFC_OFFSET_WRPR_STAT (0x18) /* Current Nand Flash Write
> + Protection Status */
> +#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation
> + Configuration 1 */
> +#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation
> + Configuration 2 */
> +
Why do you need an extra definitions for the NFC controller when we have
already one general for all i.MX ? What you define here can be found in
include/fsl_nfc.h, and the NFC controller for i.MX27 is supported as well.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
next prev parent reply other threads:[~2012-12-07 14:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-01 10:44 [U-Boot] [PATCH v3 0/3] apf27: add support of armadeus apf27 Philippe Reynes
2012-12-01 10:44 ` [U-Boot] [PATCH v3 1/3] apf27: add missing constant to mx27 Philippe Reynes
2012-12-07 14:01 ` Stefano Babic [this message]
2012-12-01 10:44 ` [U-Boot] [PATCH v2 2/3] apf27: add support for the armadeus APF27 board Philippe Reynes
2012-12-07 15:25 ` Stefano Babic
2012-12-01 10:44 ` [U-Boot] [PATCH v3 3/3] apf27: add FPGA support for the apf27 board Philippe Reynes
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=50C1F6AE.8080805@denx.de \
--to=sbabic@denx.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.