From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjVeH-0006PQ-EU for qemu-devel@nongnu.org; Fri, 14 Dec 2012 08:49:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TjVeF-0000vb-W1 for qemu-devel@nongnu.org; Fri, 14 Dec 2012 08:49:57 -0500 Message-ID: <50CB2E80.8010809@suse.de> Date: Fri, 14 Dec 2012 14:49:52 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1355487236-27451-1-git-send-email-agraf@suse.de> <1355487236-27451-11-git-send-email-agraf@suse.de> In-Reply-To: <1355487236-27451-11-git-send-email-agraf@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Bharat Bhushan , "qemu-ppc@nongnu.org List" , qemu-devel qemu-devel , Bharat Bhushan Am 14.12.2012 13:13, schrieb Alexander Graf: > From: Bharat Bhushan >=20 > PCI Root complex have TYPE-1 configuration header while PCI endpoint > have type-0 configuration header. The type-1 configuration header have > a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci > address space to CCSR address space. This can used for 2 purposes: 1) > for MSI interrupt generation 2) Allow CCSR registers access when config= ured > as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. >=20 > What I observed is that when guest read the size of BAR0 of host contro= ller > configuration header (TYPE1 header) then it always reads it as 0. When > looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controlle= r > device registering BAR0. I do not find any other controller also doing = so > may they do not use BAR0. >=20 > There are two issues when BAR0 is not there (which I can think of): > 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) an= d > when reading the size of BAR0, it should give size as per real h/w. >=20 > 2) Do we need this BAR0 inbound address translation? > When BAR0 is of non-zero size then it will be configured for PC= I > address space to local address(CCSR) space translation on inbound acces= s. > The primary use case is for MSI interrupt generation. The device is > configured with an address offsets in PCI address space, which will be > translated to MSI interrupt generation MPIC registers. Currently I do > not understand the MSI interrupt generation mechanism in QEMU and also > IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. > But this BAR0 will be used when using MSI on e500. >=20 > I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, > but i do not see these being used for address translation. > So far that works because pci address space and local address space are= 1:1 > mapped. BAR0 inbound translation + ATMU translation will complete the a= ddress > translation of inbound traffic. >=20 > Signed-off-by: Bharat Bhushan > [agraf: fix double variable assignment w/o read] > Signed-off-by: Alexander Graf Reviewed-by: Andreas F=E4rber Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg