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Date: Sat, 15 Dec 2012 14:17:26 -0800
From: "H. Peter Anvin" <hpa@zytor.com>
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Subject: Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update
 ucode on Intel's CPU
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On 12/15/2012 02:13 PM, Yinghai Lu wrote:
>
> AMD system could have all mem between TOLM and TOHM all WB, and don
> need to set them in MTRRs entries.
>

I include the TOM2 mechanism in the overall umbrella of MTRRs for this 
purpose.

> and also your switchover change that handle cross 1G, and 512g, and it
> is not 1G aligned.
> for example, if kernel at 4095G+512M, it will map from 4095G+512M to
> 4096G + 512M.

That is for the kernel region itself (that code is actually unchanged 
from the current code), and yes, we could cap that one to _end if there 
are systems which have bugs in that area.  The dynamic page tables map 
1G aligned at a time.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.