From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Subject: Re: [PATCH V2 1/2] ARM: tegra: update the cache maintenance order
 for CPU shutdown
Date: Thu, 03 Jan 2013 10:19:15 -0700
Message-ID: <50E5BD93.6060302@wwwdotorg.org>
References: <1357195380-5494-1-git-send-email-josephl@nvidia.com>
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To: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
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On 01/02/2013 11:42 PM, Joseph Lo wrote:
> Updating the cache maintenance order before CPU shutdown when doing CPU
> hotplug.
> The old order:
> * clean L1 by flush_cache_all
> * exit SMP
> * CPU shutdown
> Adapt to:
> * disable L1 data cache by clear C bit
> * clean L1 by v7_flush_dcache_louis
> * exit SMP
> * CPU shutdown
> 
> For CPU hotplug case, it's no need to do "flush_cache_all". And we should
> disable L1 data cache before clean L1 data cache. Then leaving the SMP
> coherency.

The series, applied to Tegra's for-3.9/soc branch.

From mboxrd@z Thu Jan  1 00:00:00 1970
From: swarren@wwwdotorg.org (Stephen Warren)
Date: Thu, 03 Jan 2013 10:19:15 -0700
Subject: [PATCH V2 1/2] ARM: tegra: update the cache maintenance order
 for CPU shutdown
In-Reply-To: <1357195380-5494-1-git-send-email-josephl@nvidia.com>
References: <1357195380-5494-1-git-send-email-josephl@nvidia.com>
Message-ID: <50E5BD93.6060302@wwwdotorg.org>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On 01/02/2013 11:42 PM, Joseph Lo wrote:
> Updating the cache maintenance order before CPU shutdown when doing CPU
> hotplug.
> The old order:
> * clean L1 by flush_cache_all
> * exit SMP
> * CPU shutdown
> Adapt to:
> * disable L1 data cache by clear C bit
> * clean L1 by v7_flush_dcache_louis
> * exit SMP
> * CPU shutdown
> 
> For CPU hotplug case, it's no need to do "flush_cache_all". And we should
> disable L1 data cache before clean L1 data cache. Then leaving the SMP
> coherency.

The series, applied to Tegra's for-3.9/soc branch.