From: David Daney <ddaney.cavm@gmail.com>
To: "Steven J. Hill" <sjhill@mips.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, jchandra@broadcom.com
Subject: Re: [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
Date: Fri, 04 Jan 2013 10:14:16 -0800 [thread overview]
Message-ID: <50E71BF8.3050308@gmail.com> (raw)
In-Reply-To: <1357322355-31622-1-git-send-email-sjhill@mips.com>
On 01/04/2013 09:59 AM, Steven J. Hill wrote:
> From: "Steven J. Hill" <sjhill@mips.com>
>
> The EXT and INS instructions can be used to decrease code size and
> thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores.
>
> Signed-off-by: Steven J. Hill <sjhill@mips.com>
[...]
> +#ifdef CONFIG_64BIT
> + (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1));
> +#else
> + (PGDIR_SHIFT - PAGE_SHIFT - 1));
> +#endif
> + UASM_i_INS(p, ptr, tmp, (PTE_T_LOG2 + 1),
As far as I can tell, (PAGE_SHIFT - PTE_ORDER - PTE_T_LOG2 - 1) and
(PGDIR_SHIFT - PAGE_SHIFT - 1) are the same thing. So why the two cases?
Can you give an example of where they might differ?
David Daney
next prev parent reply other threads:[~2013-01-04 18:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-04 17:59 [PATCH v3] MIPS: Optimise TLB handlers for MIPS32/64 R2 cores Steven J. Hill
2013-01-04 18:14 ` David Daney [this message]
2013-01-04 18:24 ` Hill, Steven
2013-01-04 19:51 ` Jayachandran C.
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