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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd07fa80csm13080296f8f.13.2025.02.12.03.43.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2025 03:43:06 -0800 (PST) Message-ID: <50ba4e4b-4124-46bb-bb84-4758ce9c5e66@linaro.org> Date: Wed, 12 Feb 2025 12:43:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum To: Thomas Huth , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, "Edgar E. Iglesias" , Alistair Francis , Richard Henderson , Markus Armbruster , qemu-arm@nongnu.org, =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= References: <20250212112413.37553-1-philmd@linaro.org> <20250212112413.37553-2-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 12/2/25 12:37, Thomas Huth wrote: > On 12/02/2025 12.24, Philippe Mathieu-Daudé wrote: >> Introduce the EndianMode type and the DEFINE_PROP_ENDIAN() macros. >> Endianness can be BIG, LITTLE or unspecified (default). >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   qapi/common.json                    | 16 ++++++++++++++++ >>   include/hw/qdev-properties-system.h |  7 +++++++ >>   hw/core/qdev-properties-system.c    | 11 +++++++++++ >>   3 files changed, 34 insertions(+) >> >> diff --git a/qapi/common.json b/qapi/common.json >> index 6ffc7a37890..217feaaf683 100644 >> --- a/qapi/common.json >> +++ b/qapi/common.json >> @@ -212,3 +212,19 @@ >>   ## >>   { 'struct': 'HumanReadableText', >>     'data': { 'human-readable-text': 'str' } } >> + >> +## >> +# @EndianMode: >> +# >> +# An enumeration of three options: little, big, and unspecified >> +# >> +# @little: Little endianness >> +# >> +# @big: Big endianness >> +# >> +# @unspecified: Endianness not specified >> +# >> +# Since: 10.0 >> +## >> +{ 'enum': 'EndianMode', >> +  'data': [ 'little', 'big', 'unspecified' ] } > > Should 'unspecified' come first? ... so that it gets the value 0, i.e. > when someone forgets to properly initialize a related variable, the > chances are higher that it ends up as "unspecified" than as "little" ? Hmm but then in this series the dual-endianness regions are defined as: +static const MemoryRegionOps pic_ops[2] = { + [0 ... 1] = { + .read = pic_read, + .write = pic_write, + .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + /* + * All XPS INTC registers are accessed through the PLB interface. + * The base address for these registers is provided by the + * configuration parameter, C_BASEADDR. Each register is 32 bits + * although some bits may be unused and is accessed on a 4-byte + * boundary offset from the base address. + */ + .min_access_size = 4, + .max_access_size = 4, + }, }, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } + [ENDIAN_MODE_BIG].endianness = DEVICE_BIG_ENDIAN, + [ENDIAN_MODE_LITTLE].endianness = DEVICE_LITTLE_ENDIAN, }; We could declare the array using the confusing __MAX definition (at the price of wasting the ENDIAN_MODE_UNSPECIFIED entry) as: static const MemoryRegionOps pic_ops[ENDIAN_MODE__MAX - 1] { } WDYT? > Apart from that: > Reviewed-by: Thomas Huth > Thanks!