From: Yijing Wang <wangyijing@huawei.com>
To: Randy Dunlap <rdunlap@infradead.org>
Cc: Rob Landley <rob@landley.net>,
Bjorn Helgaas <bhelgaas@google.com>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, Jon Mason <jdmason@kudzu.us>,
<linux-pci@vger.kernel.org>,
Andrew Murray <andrew.murray@arm.com>,
Hanjun Guo <guohanjun@huawei.com>, <jiang.liu@huawei.com>
Subject: Re: [Update][PATCH] PCI: Document PCIE BUS MPS parameters
Date: Thu, 24 Jan 2013 10:20:47 +0800 [thread overview]
Message-ID: <51009A7F.6050104@huawei.com> (raw)
In-Reply-To: <51009645.5040406@infradead.org>
On 2013/1/24 10:02, Randy Dunlap wrote:
> On 01/23/13 17:55, Yijing Wang wrote:
>> Hi Randy,
>> Thanks for your review and comments! please refer to inlined comments below.
>>
>> On 2013/1/24 7:39, Randy Dunlap wrote:
>>> On 01/23/13 04:28, Yijing Wang wrote:
>
>>>
>>> What is (are) MRRS?
>>
>> MRRS is "Max Read Request Size" and MPS is "Max Payload Size".
>> Need use "Max Read Request Size" instead of MRRS ?
>
> Where is MRRS documented?
The description of MRRS can be found at PCIe Spec 2.0/3.0 7.8.4 Device Control Register.
>
> I would probably do it like so:
>
> Also set MRRS (Max Read Request Size) to the ....
Hmm, I will explain MPS and MRRS when they appear first time like,
pcie_bus_tune_off Disable PCIe MPS (Max Payload Size) turning and using
the BIOS-configured MPS defaults.
pcie_bus_perf ......Also set MRRS (Max Read Request Size) to the......
Thanks!
Yijing
>
--
Thanks!
Yijing
prev parent reply other threads:[~2013-01-24 2:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-23 12:28 [Update][PATCH] PCI: Document PCIE BUS MPS parameters Yijing Wang
2013-01-23 23:39 ` Randy Dunlap
2013-01-24 1:55 ` Yijing Wang
2013-01-24 2:02 ` Randy Dunlap
2013-01-24 2:20 ` Yijing Wang [this message]
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