[PATCHv1 for soc 0/5] Enabling socfpga on hardware

[PATCHv1 for soc 0/5] Enabling socfpga on hardware

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Hi,

Up until this point, support for socfpga has only been for a virtual target environment.
Here are a set of patches that enables socfpga on actual hardware.

patch: arm: Add v7_invalidate_l1 to cache-v7.S  should be of some interest.
When enabling SMP on ARMv7 hardware on socfpga, the call to v7_flush_dcache_all was
making the main CPU lost. On socfpga, as well as IMX, SHMOBILE, and TEGRA the call
to v7_invalidate_l1 was required.

Thanks,
Dinh

Dinh Nguyen (5):
  arm: socfpga: Add new device tree source for actual socfpga HW
  arm: socfpga: Add clock entries to socfpga.dtsi
  arm: socfpga: Add entries to enable make dtbs socfpga
  arm: Add v7_invalidate_l1 to cache-v7.S
  arm: socfpga: Add SMP support for actual socfpga harware

 arch/arm/boot/dts/Makefile             |    2 ++
 arch/arm/boot/dts/socfpga.dtsi         |   59 ++++++++++++++++++++++++-------
 arch/arm/boot/dts/socfpga_cyclone5.dts |   28 ++++++++++++++-
 arch/arm/boot/dts/socfpga_vt.dts       |   60 ++++++++++++++++++++++++++++++++
 arch/arm/configs/socfpga_defconfig     |    1 +
 arch/arm/mach-imx/headsmp.S            |   47 -------------------------
 arch/arm/mach-shmobile/headsmp.S       |   48 -------------------------
 arch/arm/mach-socfpga/core.h           |    4 ++-
 arch/arm/mach-socfpga/headsmp.S        |   14 +++++---
 arch/arm/mach-socfpga/platsmp.c        |    3 +-
 arch/arm/mach-socfpga/socfpga.c        |   17 +++++++++
 arch/arm/mach-tegra/headsmp.S          |   43 -----------------------
 arch/arm/mm/cache-v7.S                 |   47 +++++++++++++++++++++++++
 13 files changed, 216 insertions(+), 157 deletions(-)
 create mode 100644 arch/arm/boot/dts/socfpga_vt.dts

-- 
1.7.9.5

[PATCHv1 for soc 1/5] arm: socfpga: Add new device tree source for actual socfpga HW

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/boot/dts/socfpga.dtsi         |   22 ++++++------
 arch/arm/boot/dts/socfpga_cyclone5.dts |   28 ++++++++++++++-
 arch/arm/boot/dts/socfpga_vt.dts       |   60 ++++++++++++++++++++++++++++++++
 arch/arm/mach-socfpga/socfpga.c        |    1 +
 4 files changed, 98 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/boot/dts/socfpga_vt.dts

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 19aec42..936d230 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -25,6 +25,10 @@
 		ethernet0 = &gmac0;
 		serial0 = &uart0;
 		serial1 = &uart1;
+		timer0 = &timer0;
+		timer1 = &timer1;
+		timer2 = &timer2;
+		timer3 = &timer3;
 	};
 
 	cpus {
@@ -98,47 +102,41 @@
 			interrupts = <1 13 0xf04>;
 		};
 
-		timer0: timer at ffc08000 {
+		timer0: timer0 at ffc08000 {
 			compatible = "snps,dw-apb-timer-sp";
 			interrupts = <0 167 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffc08000 0x1000>;
 		};
 
-		timer1: timer at ffc09000 {
+		timer1: timer1 at ffc09000 {
 			compatible = "snps,dw-apb-timer-sp";
 			interrupts = <0 168 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffc09000 0x1000>;
 		};
 
-		timer2: timer at ffd00000 {
+		timer2: timer2 at ffd00000 {
 			compatible = "snps,dw-apb-timer-osc";
 			interrupts = <0 169 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffd00000 0x1000>;
 		};
 
-		timer3: timer at ffd01000 {
+		timer3: timer3 at ffd01000 {
 			compatible = "snps,dw-apb-timer-osc";
 			interrupts = <0 170 4>;
-			clock-frequency = <200000000>;
 			reg = <0xffd01000 0x1000>;
 		};
 
-		uart0: uart at ffc02000 {
+		uart0: serial0 at ffc02000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xffc02000 0x1000>;
-			clock-frequency = <7372800>;
 			interrupts = <0 162 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 		};
 
-		uart1: uart at ffc03000 {
+		uart1: serial1 at ffc03000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xffc03000 0x1000>;
-			clock-frequency = <7372800>;
 			interrupts = <0 163 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index ab7e4a9..1a6d088 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -29,6 +29,32 @@
 	memory {
 		name = "memory";
 		device_type = "memory";
-		reg = <0x0 0x10000000>; /* 256MB */
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		timer0 at ffc08000 {
+			clock-frequency = <100000000>;
+		};
+
+		timer1 at ffc09000 {
+			clock-frequency = <100000000>;
+		};
+
+		timer2 at ffd00000 {
+			clock-frequency = <25000000>;
+		};
+
+		timer3 at ffd01000 {
+			clock-frequency = <25000000>;
+		};
+
+		serial0 at ffc02000 {
+			clock-frequency = <100000000>;
+		};
+
+		serial1 at ffc03000 {
+			clock-frequency = <100000000>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
new file mode 100644
index 0000000..df3551f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+	model = "Altera SOCFPGA VT";
+	compatible = "altr,socfpga-vt";
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1 GB */
+	};
+
+	soc {
+		timer0 at ffc08000 {
+			clock-frequency = <7000000>;
+		};
+
+		timer1 at ffc09000 {
+			clock-frequency = <7000000>;
+		};
+
+		timer2 at ffd00000 {
+			clock-frequency = <7000000>;
+		};
+
+		timer3 at ffd01000 {
+			clock-frequency = <7000000>;
+		};
+
+		serial0 at ffc02000 {
+			clock-frequency = <7372800>;
+		};
+
+		serial1 at ffc03000 {
+			clock-frequency = <7372800>;
+		};
+	};
+};
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 6732924..198f491 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -99,6 +99,7 @@ static void __init socfpga_cyclone5_init(void)
 static const char *altera_dt_match[] = {
 	"altr,socfpga",
 	"altr,socfpga-cyclone5",
+	"altr,socfpga-vt",
 	NULL
 };
 
-- 
1.7.9.5

[PATCHv1 for soc 1/5] arm: socfpga: Add new device tree source for actual socfpga HW

[Pavel Machek]

Hi!

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Up to this point, support for socfpga has only been on a virtual
> platform. Now that actual hardware is available, we add the appropriate
> device tree source files.

Wow, actual hardware :-). Can I get one?

> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: Pavel Machek <pavel@denx.de>

I tested it on 3.7-rc2-based tree, as it is newest I have around. It
seems to work ok. [Do you have newer git tree somewhere?]

Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>

									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 1/5] arm: socfpga: Add new device tree source for actual socfpga HW

[Dinh Nguyen]

Hi Pavel,

On Fri, 2013-01-25 at 15:22 +0100, Pavel Machek wrote:
> Hi!
> 
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Up to this point, support for socfpga has only been on a virtual
> > platform. Now that actual hardware is available, we add the appropriate
> > device tree source files.
> 
> Wow, actual hardware :-). Can I get one?

Ramping up production now...
> 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Olof Johansson <olof@lixom.net>
> > Cc: Pavel Machek <pavel@denx.de>
> 
> I tested it on 3.7-rc2-based tree, as it is newest I have around. It
> seems to work ok. [Do you have newer git tree somewhere?]
> 
> Tested-by: Pavel Machek <pavel@denx.de>
> Reviewed-by: Pavel Machek <pavel@denx.de>

Thanks,
Dinh
> 
> 									Pavel
> 

[PATCHv1 for soc 1/5] arm: socfpga: Add new device tree source for actual socfpga HW

[Olof Johansson]

Hi,

Nit below.

On Thu, Jan 24, 2013 at 07:00:29PM -0600, dinguyen at altera.com wrote:
> diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
> new file mode 100644
> index 0000000..df3551f
> --- /dev/null
> +++ b/arch/arm/boot/dts/socfpga_vt.dts
> @@ -0,0 +1,60 @@
> +/*
> + *  Copyright (C) 2013 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/dts-v1/;
> +/include/ "socfpga.dtsi"
> +
> +/ {
> +	model = "Altera SOCFPGA VT";
> +	compatible = "altr,socfpga-vt";
> +
[...]
> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
> index 6732924..198f491 100644
> --- a/arch/arm/mach-socfpga/socfpga.c
> +++ b/arch/arm/mach-socfpga/socfpga.c
> @@ -99,6 +99,7 @@ static void __init socfpga_cyclone5_init(void)
>  static const char *altera_dt_match[] = {
>  	"altr,socfpga",
>  	"altr,socfpga-cyclone5",
> +	"altr,socfpga-vt",
>  	NULL
>  };

If you add "altr,socfpga" as a second compatible field in the dts for
the board, then you won't have to update the board C file every time you
add a new board dts (as long as you don't need to do something special
with that board).


-Olof

[PATCHv1 for soc 2/5] arm: socfpga: Add clock entries to socfpga.dtsi

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/boot/dts/socfpga.dtsi |   37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 936d230..688729f 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -78,6 +78,43 @@
 			};
 		};
 
+		clkmgr at ffd04000 {
+			compatible = "altr, clk-mgr";
+			reg = <0xffd04000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				osc1: oscillator {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <50000000>;
+				};
+
+				mainpll: mainpll {
+					#clock-cells = <0>;
+					compatible = "altr,main-pll-clock";
+					clocks = <&osc1>;
+					reg = <0x40>;
+				};
+
+				perpll: perpll {
+					#clock-cells = <0>;
+					compatible = "altr,per-pll-clock";
+					clocks = <&osc1>;
+					reg = <0x80>;
+				};
+
+				sdrampll: sdrampll {
+					#clock-cells = <0>;
+					compatible = "altr,sdram-pll-clock";
+					clocks = <&osc1>;
+					reg = <0xC0>;
+				};
+			};
+		};
+
 		gmac0: stmmac at ff700000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff700000 0x2000>;
-- 
1.7.9.5

[PATCHv1 for soc 2/5] arm: socfpga: Add clock entries to socfpga.dtsi

[Olof Johansson]

Hi,

On Thu, Jan 24, 2013 at 07:00:30PM -0600, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: Pavel Machek <pavel@denx.de>
> ---
>  arch/arm/boot/dts/socfpga.dtsi |   37 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 936d230..688729f 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -78,6 +78,43 @@
>  			};
>  		};
>  
> +		clkmgr at ffd04000 {
> +			compatible = "altr, clk-mgr";


No space after "altr,". Also, this should have documented bindings under
Documentation/device-tree/bindings (and those should be cc:d to the appropriate
maintainers).


-Olof

[PATCHv1 for soc 2/5] arm: socfpga: Add clock entries to socfpga.dtsi

[Pavel Machek]

Hi!

> On Thu, Jan 24, 2013 at 07:00:30PM -0600, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Olof Johansson <olof@lixom.net>
> > Cc: Pavel Machek <pavel@denx.de>
> > ---
> >  arch/arm/boot/dts/socfpga.dtsi |   37 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index 936d230..688729f 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -78,6 +78,43 @@
> >  			};
> >  		};
> >  
> > +		clkmgr at ffd04000 {
> > +			compatible = "altr, clk-mgr";
> 
> 
> No space after "altr,". Also, this should have documented bindings under
> Documentation/device-tree/bindings (and those should be cc:d to the appropriate
> maintainers).

Are the clk-mgr entries used in this series? I see only definition in
device tree, but no usage... Thanks,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 3/5] arm: socfpga: Add entries to enable make dtbs socfpga

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/boot/dts/Makefile |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5ebb44f..1b8276c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a7740-armadillo800eva.dtb \
 	sh73a0-kzm9g.dtb \
 	sh7372-mackerel.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
 dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
-- 
1.7.9.5

[PATCHv1 for soc 3/5] arm: socfpga: Add entries to enable make dtbs socfpga

[Pavel Machek]

> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
>  	r8a7740-armadillo800eva.dtb \
>  	sh73a0-kzm9g.dtb \
>  	sh7372-mackerel.dtb
> +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
> +	socfpga_vt.dtb
>  dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
>  	spear1340-evb.dtb
>  dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \

This allows me to remove manual dtb invocation from the build
scripts. Good.

For 2,3/5:

Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 3/5] arm: socfpga: Add entries to enable make dtbs socfpga

[Dinh Nguyen]

Hi Pavel,

On Fri, 2013-01-25 at 16:13 +0100, Pavel Machek wrote:
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
> >  	r8a7740-armadillo800eva.dtb \
> >  	sh73a0-kzm9g.dtb \
> >  	sh7372-mackerel.dtb
> > +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
> > +	socfpga_vt.dtb
> >  dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
> >  	spear1340-evb.dtb
> >  dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
> 
> This allows me to remove manual dtb invocation from the build
> scripts. Good.
> 
> For 2,3/5:
> 
> Tested-by: Pavel Machek <pavel@denx.de>
> Reviewed-by: Pavel Machek <pavel@denx.de>

Thanks,
Dinh
> 
> 									Pavel

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

mach-socfpga is another platform that needs to use
v7_invalidate_l1 to bringup additional cores. There was a comment that
the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
 arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
 arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
 arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
 4 files changed, 47 insertions(+), 138 deletions(-)

diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb..921fc15 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -17,53 +17,6 @@
 
 	.section ".text.head", "ax"
 
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0
-
-	ldr	r1, =0x7fff
-	and	r2, r1, r0, lsr #13
-
-	ldr	r1, =0x3ff
-
-	and	r3, r1, r0, lsr #3	@ NumWays - 1
-	add	r2, r2, #1		@ NumSets
-
-	and	r0, r0, #0x7
-	add	r0, r0, #4	@ SetShift
-
-	clz	r1, r3		@ WayShift
-	add	r4, r3, #1	@ NumWays
-1:	sub	r2, r2, #1	@ NumSets--
-	mov	r3, r4		@ Temp = NumWays
-2:	subs	r3, r3, #1	@ Temp--
-	mov	r5, r3, lsl r1
-	mov	r6, r2, lsl r0
-	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-	mcr	p15, 0, r5, c7, c6, 2
-	bgt	2b
-	cmp	r2, #0
-	bgt	1b
-	dsb
-	isb
-	mov	pc, lr
-ENDPROC(v7_invalidate_l1)
-
 #ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
 	bl	v7_invalidate_l1
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index b202c12..96001fd 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,54 +16,6 @@
 
 	__CPUINIT
 
-/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
- *
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
-	mcr	p15, 2, r0, c0, c0, 0
-	mrc	p15, 1, r0, c0, c0, 0
-
-	ldr	r1, =0x7fff
-	and	r2, r1, r0, lsr #13
-
-	ldr	r1, =0x3ff
-
-	and	r3, r1, r0, lsr #3	@ NumWays - 1
-	add	r2, r2, #1		@ NumSets
-
-	and	r0, r0, #0x7
-	add	r0, r0, #4	@ SetShift
-
-	clz	r1, r3		@ WayShift
-	add	r4, r3, #1	@ NumWays
-1:	sub	r2, r2, #1	@ NumSets--
-	mov	r3, r4		@ Temp = NumWays
-2:	subs	r3, r3, #1	@ Temp--
-	mov	r5, r3, lsl r1
-	mov	r6, r2, lsl r0
-	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-	mcr	p15, 0, r5, c7, c6, 2
-	bgt	2b
-	cmp	r2, #0
-	bgt	1b
-	dsb
-	isb
-	mov	pc, lr
-ENDPROC(v7_invalidate_l1)
-
 ENTRY(shmobile_invalidate_start)
 	bl	v7_invalidate_l1
 	b	secondary_startup
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 4a317fa..fb082c4 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -18,49 +18,6 @@
         .section ".text.head", "ax"
 	__CPUINIT
 
-/*
- * Tegra specific entry point for secondary CPUs.
- *   The secondary kernel init calls v7_flush_dcache_all before it enables
- *   the L1; however, the L1 comes out of reset in an undefined state, so
- *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- *   of cache lines with uninitialized data and uninitialized tags to get
- *   written out to memory, which does really unpleasant things to the main
- *   processor.  We fix this by performing an invalidate, rather than a
- *   clean + invalidate, before jumping into the kernel.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-
-        ldr     r1, =0x3ff
-
-        and     r3, r1, r0, lsr #3  @ NumWays - 1
-        add     r2, r2, #1          @ NumSets
-
-        and     r0, r0, #0x7
-        add     r0, r0, #4          @ SetShift
-
-        clz     r1, r3              @ WayShift
-        add     r4, r3, #1          @ NumWays
-1:      sub     r2, r2, #1          @ NumSets--
-        mov     r3, r4              @ Temp = NumWays
-2:      subs    r3, r3, #1          @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
-
 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 7539ec2..a7f7893 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -19,6 +19,53 @@
 #include "proc-macros.S"
 
 /*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.
+ */
+ENTRY(v7_invalidate_l1)
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
+       mcr     p15, 2, r0, c0, c0, 0
+       mrc     p15, 1, r0, c0, c0, 0
+
+       ldr     r1, =0x7fff
+       and     r2, r1, r0, lsr #13
+
+       ldr     r1, =0x3ff
+
+       and     r3, r1, r0, lsr #3      @ NumWays - 1
+       add     r2, r2, #1              @ NumSets
+
+       and     r0, r0, #0x7
+       add     r0, r0, #4      @ SetShift
+
+       clz     r1, r3          @ WayShift
+       add     r4, r3, #1      @ NumWays
+1:     sub     r2, r2, #1      @ NumSets--
+       mov     r3, r4          @ Temp = NumWays
+2:     subs    r3, r3, #1      @ Temp--
+       mov     r5, r3, lsl r1
+       mov     r6, r2, lsl r0
+       orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+       mcr     p15, 0, r5, c7, c6, 2
+       bgt     2b
+       cmp     r2, #0
+       bgt     1b
+       dsb
+       isb
+       mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+
+/*
  *	v7_flush_icache_all()
  *
  *	Flush the whole I-cache.
-- 
1.7.9.5

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Simon Horman]

On Thu, Jan 24, 2013 at 07:00:32PM -0600, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> mach-socfpga is another platform that needs to use
> v7_invalidate_l1 to bringup additional cores. There was a comment that
> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Pavel Machek <pavel@denx.de>

mach-shmobile portion:

Acked-by: Simon Horman <horms+renesas@verge.net.au>

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Simon Horman]

On Fri, Jan 25, 2013 at 01:15:03PM +0900, Simon Horman wrote:
> On Thu, Jan 24, 2013 at 07:00:32PM -0600, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > mach-socfpga is another platform that needs to use
> > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Cc: Olof Johansson <olof@lixom.net>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Rob Herring <rob.herring@calxeda.com>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Simon Horman <horms@verge.net.au>
> > Cc: Magnus Damm <magnus.damm@gmail.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Pavel Machek <pavel@denx.de>
> 
> mach-shmobile portion:
> 
> Acked-by: Simon Horman <horms+renesas@verge.net.au>

For the record, I tested this on the kzm9g, kzm9d and marzen boards.

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Dinh Nguyen]

Hi Simon,

On Fri, 2013-01-25 at 13:35 +0900, Simon Horman wrote:
> On Fri, Jan 25, 2013 at 01:15:03PM +0900, Simon Horman wrote:
> > On Thu, Jan 24, 2013 at 07:00:32PM -0600, dinguyen at altera.com wrote:
> > > From: Dinh Nguyen <dinguyen@altera.com>
> > > 
> > > mach-socfpga is another platform that needs to use
> > > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> > > 
> > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > > Cc: Arnd Bergmann <arnd@arndb.de>
> > > Cc: Russell King <linux@arm.linux.org.uk>
> > > Cc: Olof Johansson <olof@lixom.net>
> > > Cc: Thomas Gleixner <tglx@linutronix.de>
> > > Cc: Rob Herring <rob.herring@calxeda.com>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Simon Horman <horms@verge.net.au>
> > > Cc: Magnus Damm <magnus.damm@gmail.com>
> > > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > > Cc: Pavel Machek <pavel@denx.de>
> > 
> > mach-shmobile portion:
> > 
> > Acked-by: Simon Horman <horms+renesas@verge.net.au>
> 
> For the record, I tested this on the kzm9g, kzm9d and marzen boards.

Thanks,
Dinh
> 

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Stephen Warren]

On 01/24/2013 05:00 PM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> mach-socfpga is another platform that needs to use
> v7_invalidate_l1 to bringup additional cores. There was a comment that
> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S

> -ENTRY(v7_invalidate_l1)
> -        mov     r0, #0

Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that
function from headsmp.S to reset-handler.S, so this patch will conflict.
How do you want to handle that?

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Pavel Machek]

On Thu 2013-01-24 20:42:08, Stephen Warren wrote:
> On 01/24/2013 05:00 PM, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > mach-socfpga is another platform that needs to use
> > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> 
> > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
> 
> > -ENTRY(v7_invalidate_l1)
> > -        mov     r0, #0
> 
> Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that
> function from headsmp.S to reset-handler.S, so this patch will conflict.
> How do you want to handle that?

Drop the patch from Tegra tree and merge this one there? Having three
copies of code is not nice to start with, no matter where it is...
								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Stephen Warren]

On 01/28/2013 03:45 AM, Pavel Machek wrote:
> On Thu 2013-01-24 20:42:08, Stephen Warren wrote:
>> On 01/24/2013 05:00 PM, dinguyen at altera.com wrote:
>>> From: Dinh Nguyen <dinguyen@altera.com>
>>>
>>> mach-socfpga is another platform that needs to use
>>> v7_invalidate_l1 to bringup additional cores. There was a comment that
>>> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
>>
>>> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
>>
>>> -ENTRY(v7_invalidate_l1)
>>> -        mov     r0, #0
>>
>> Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that
>> function from headsmp.S to reset-handler.S, so this patch will conflict.
>> How do you want to handle that?
> 
> Drop the patch from Tegra tree and merge this one there? Having three
> copies of code is not nice to start with, no matter where it is...

Well, I guess for other reasons rebasing the Tegra tree is useful for a
few dependencies, so I'll drop that part of the patch which moves
v7_invalidate_l1() from one file to another, so there shouldn't be any
conflicts, and you can feel free to take this series through whatever
tree you want.

I haven't tested this patch yet though, to see whether the slight
differences in the code in your patch mentioned in the other sub-thread
affect Tegra at all. Hopefully I can test this later today.

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Dinh Nguyen]

Hi Stephen,

On Mon, 2013-01-28 at 10:27 -0700, Stephen Warren wrote:
> On 01/28/2013 03:45 AM, Pavel Machek wrote:
> > On Thu 2013-01-24 20:42:08, Stephen Warren wrote:
> >> On 01/24/2013 05:00 PM, dinguyen at altera.com wrote:
> >>> From: Dinh Nguyen <dinguyen@altera.com>
> >>>
> >>> mach-socfpga is another platform that needs to use
> >>> v7_invalidate_l1 to bringup additional cores. There was a comment that
> >>> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> >>
> >>> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
> >>
> >>> -ENTRY(v7_invalidate_l1)
> >>> -        mov     r0, #0
> >>
> >> Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that
> >> function from headsmp.S to reset-handler.S, so this patch will conflict.
> >> How do you want to handle that?
> > 
> > Drop the patch from Tegra tree and merge this one there? Having three
> > copies of code is not nice to start with, no matter where it is...
> 
> Well, I guess for other reasons rebasing the Tegra tree is useful for a
> few dependencies, so I'll drop that part of the patch which moves
> v7_invalidate_l1() from one file to another, so there shouldn't be any
> conflicts, and you can feel free to take this series through whatever
> tree you want.
> 
> I haven't tested this patch yet though, to see whether the slight
> differences in the code in your patch mentioned in the other sub-thread
> affect Tegra at all. Hopefully I can test this later today.

Shawn Guo mentioned that the instruction to invalidate I-Cache is
unnecessary becauce of this commit: 612539e (ARM: 7296/1: proc-v7.S:
remove HARVARD_CACHE preprocessor guards)

So I'll send v2 without the extra instruction.

Thanks,
Dinh
> 

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Santosh Shilimkar]

On Friday 25 January 2013 06:30 AM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
>
> mach-socfpga is another platform that needs to use
> v7_invalidate_l1 to bringup additional cores. There was a comment that
> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
>
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Pavel Machek <pavel@denx.de>
> ---
>   arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
>   arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
>   arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
>   arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
>   4 files changed, 47 insertions(+), 138 deletions(-)
>
Does yor kernel skips the decompresser. Am just curious about
what you describe above since you should see the issue already
at decompresser. Your boot loader is expected to clean and
invalidating the caches before jumping into the kernel.

Regards,
Santosh

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Dinh Nguyen]

Hi Santosh,

On Fri, 2013-01-25 at 13:43 +0530, Santosh Shilimkar wrote:
> On Friday 25 January 2013 06:30 AM, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> >
> > mach-socfpga is another platform that needs to use
> > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> >
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Russell King <linux@arm.linux.org.uk>
> > Cc: Olof Johansson <olof@lixom.net>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Rob Herring <rob.herring@calxeda.com>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Simon Horman <horms@verge.net.au>
> > Cc: Magnus Damm <magnus.damm@gmail.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Pavel Machek <pavel@denx.de>
> > ---
> >   arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
> >   arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
> >   arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
> >   arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
> >   4 files changed, 47 insertions(+), 138 deletions(-)
> >
> Does yor kernel skips the decompresser. Am just curious about
> what you describe above since you should see the issue already
> at decompresser. Your boot loader is expected to clean and
> invalidating the caches before jumping into the kernel.

This is for bringing up the 2nd core after the main CPU is already
alive. Indeed, I did see this issue when the main CPU was coming up and
have changed the bootloader to clean and invalidate the caches.

Dinh
> 
> Regards,
> Santosh
> 
> 

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Santosh Shilimkar]

On Friday 25 January 2013 09:50 PM, Dinh Nguyen wrote:
> Hi Santosh,
>
> On Fri, 2013-01-25 at 13:43 +0530, Santosh Shilimkar wrote:
>> On Friday 25 January 2013 06:30 AM, dinguyen at altera.com wrote:
>>> From: Dinh Nguyen <dinguyen@altera.com>
>>>
>>> mach-socfpga is another platform that needs to use
>>> v7_invalidate_l1 to bringup additional cores. There was a comment that
>>> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
>>>
>>> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Russell King <linux@arm.linux.org.uk>
>>> Cc: Olof Johansson <olof@lixom.net>
>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>> Cc: Rob Herring <rob.herring@calxeda.com>
>>> Cc: Sascha Hauer <kernel@pengutronix.de>
>>> Cc: Simon Horman <horms@verge.net.au>
>>> Cc: Magnus Damm <magnus.damm@gmail.com>
>>> Cc: Stephen Warren <swarren@wwwdotorg.org>
>>> Cc: Pavel Machek <pavel@denx.de>
>>> ---
>>>    arch/arm/mach-imx/headsmp.S      |   47 -------------------------------------
>>>    arch/arm/mach-shmobile/headsmp.S |   48 --------------------------------------
>>>    arch/arm/mach-tegra/headsmp.S    |   43 ----------------------------------
>>>    arch/arm/mm/cache-v7.S           |   47 +++++++++++++++++++++++++++++++++++++
>>>    4 files changed, 47 insertions(+), 138 deletions(-)
>>>
>> Does yor kernel skips the decompresser. Am just curious about
>> what you describe above since you should see the issue already
>> at decompresser. Your boot loader is expected to clean and
>> invalidating the caches before jumping into the kernel.
>
> This is for bringing up the 2nd core after the main CPU is already
> alive. Indeed, I did see this issue when the main CPU was coming up and
> have changed the bootloader to clean and invalidate the caches.
>
Ahh. I understand it now.

Regards
Santosh

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Pavel Machek]

Hi!

> mach-socfpga is another platform that needs to use
> v7_invalidate_l1 to bringup additional cores. There was a comment that
> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

If there are three copies of code, with fourth one needed for next
platform, moving it into common code makes sense.

But... The code was not identical before the merge. Are you sure that
the differences do not hurt? At the very least, it should be mentioned
in the changelog.

Thanks,
								Pavel

> diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
> index 7e49deb..921fc15 100644
> --- a/arch/arm/mach-imx/headsmp.S
> +++ b/arch/arm/mach-imx/headsmp.S
> @@ -17,53 +17,6 @@
> -ENTRY(v7_invalidate_l1)
> -	mov	r0, #0
> -	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
> -	mcr	p15, 2, r0, c0, c0, 0
> -	mrc	p15, 1, r0, c0, c0, 0
...
> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
> index 4a317fa..fb082c4 100644
> --- a/arch/arm/mach-tegra/headsmp.S
> +++ b/arch/arm/mach-tegra/headsmp.S
> @@ -18,49 +18,6 @@
> -ENTRY(v7_invalidate_l1)
> -        mov     r0, #0
> -        mcr     p15, 2, r0, c0, c0, 0
> -        mrc     p15, 1, r0, c0, c0, 0

[Note missing mcr p15, 0, .. line.]


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Dinh Nguyen]

Hi Pavel,
On Fri, 2013-01-25 at 16:49 +0100, Pavel Machek wrote:
> Hi!
> 
> > mach-socfpga is another platform that needs to use
> > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> 
> If there are three copies of code, with fourth one needed for next
> platform, moving it into common code makes sense.
> 
> But... The code was not identical before the merge. Are you sure that
> the differences do not hurt? At the very least, it should be mentioned
> in the changelog.

Indeed, the addition of 

mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache

was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d

This adds invalidate I-Cache as well as D-Cache, which I think should be
ok for most platforms. 

Hopefully, Stephen can test and verify.

Dinh
> 
> Thanks,
> 								Pavel
> 
> > diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
> > index 7e49deb..921fc15 100644
> > --- a/arch/arm/mach-imx/headsmp.S
> > +++ b/arch/arm/mach-imx/headsmp.S
> > @@ -17,53 +17,6 @@
> > -ENTRY(v7_invalidate_l1)
> > -	mov	r0, #0
> > -	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
> > -	mcr	p15, 2, r0, c0, c0, 0
> > -	mrc	p15, 1, r0, c0, c0, 0
> ...
> > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
> > index 4a317fa..fb082c4 100644
> > --- a/arch/arm/mach-tegra/headsmp.S
> > +++ b/arch/arm/mach-tegra/headsmp.S
> > @@ -18,49 +18,6 @@
> > -ENTRY(v7_invalidate_l1)
> > -        mov     r0, #0
> > -        mcr     p15, 2, r0, c0, c0, 0
> > -        mrc     p15, 1, r0, c0, c0, 0
> 
> [Note missing mcr p15, 0, .. line.]
> 
> 

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Pavel Machek]

On Fri 2013-01-25 10:24:17, Dinh Nguyen wrote:
> Hi Pavel,
> On Fri, 2013-01-25 at 16:49 +0100, Pavel Machek wrote:
> > Hi!
> > 
> > > mach-socfpga is another platform that needs to use
> > > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> > 
> > If there are three copies of code, with fourth one needed for next
> > platform, moving it into common code makes sense.
> > 
> > But... The code was not identical before the merge. Are you sure that
> > the differences do not hurt? At the very least, it should be mentioned
> > in the changelog.
> 
> Indeed, the addition of 
> 
> mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
> 
> was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d
> 
> This adds invalidate I-Cache as well as D-Cache, which I think should be
> ok for most platforms. 
> 
> Hopefully, Stephen can test and verify.

Otherwise it works for me... and looks like a good idea.

Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>

Thanks,
								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 4/5] arm: Add v7_invalidate_l1 to cache-v7.S

[Shawn Guo]

On Fri, Jan 25, 2013 at 10:24:17AM -0600, Dinh Nguyen wrote:
> Hi Pavel,
> On Fri, 2013-01-25 at 16:49 +0100, Pavel Machek wrote:
> > Hi!
> > 
> > > mach-socfpga is another platform that needs to use
> > > v7_invalidate_l1 to bringup additional cores. There was a comment that
> > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
> > 
> > If there are three copies of code, with fourth one needed for next
> > platform, moving it into common code makes sense.
> > 
> > But... The code was not identical before the merge. Are you sure that
> > the differences do not hurt? At the very least, it should be mentioned
> > in the changelog.
> 
> Indeed, the addition of 
> 
> mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
> 
This becomes unnecessary since commit 612539e (ARM: 7296/1: proc-v7.S:
remove HARVARD_CACHE preprocessor guards) gets in.

Shawn

> was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d
> 
> This adds invalidate I-Cache as well as D-Cache, which I think should be
> ok for most platforms. 
> 

[PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
---
 arch/arm/configs/socfpga_defconfig |    1 +
 arch/arm/mach-socfpga/core.h       |    4 +++-
 arch/arm/mach-socfpga/headsmp.S    |   14 ++++++++++----
 arch/arm/mach-socfpga/platsmp.c    |    3 ++-
 arch/arm/mach-socfpga/socfpga.c    |   16 ++++++++++++++++
 5 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 4e1ce21..480ab64 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_AEABI=y
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 9941caa..5b76dd4 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_CORE_H
 #define __MACH_CORE_H
 
-extern void secondary_startup(void);
+extern void v7_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
@@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void);
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
 
+extern unsigned long cpu1start_addr;
+
 #define SOCFPGA_SCU_VIRT_BASE   0xfffec000
 
 #endif
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index f09b128..01911e8 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -13,13 +13,19 @@
 	__CPUINIT
 	.arch	armv7-a
 
-#define CPU1_START_ADDR 	        0xffd08010
-
 ENTRY(secondary_trampoline)
-	movw	r0, #:lower16:CPU1_START_ADDR
-	movt  r0, #:upper16:CPU1_START_ADDR
+	movw	r2, #:lower16:cpu1start_addr
+	movt  r2, #:upper16:cpu1start_addr
 
+	ldr	r0, [r2]
 	ldr	r1, [r0]
 	bx	r1
 
 ENTRY(secondary_trampoline_end)
+
+#ifdef CONFIG_SMP
+ENTRY(v7_secondary_startup)
+       bl      v7_invalidate_l1
+       b       secondary_startup
+ENDPROC(v7_secondary_startup)
+#endif
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 68dd1b6..c428519 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
 
 	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+	__raw_writel(virt_to_phys(v7_secondary_startup),
+		(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
 
 	flush_cache_all();
 	smp_wmb();
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 198f491..317f4c3 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,6 +29,7 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
+unsigned long cpu1start_addr;
 
 static struct map_desc scu_io_desc __initdata = {
 	.virtual	= SOCFPGA_SCU_VIRT_BASE,
@@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
+static void __init init_socfpga_vt(void)
+{
+	cpu1start_addr = 0xffd08010;
+}
+
+static void __init init_socfpga(void)
+{
+	cpu1start_addr = 0xffd080c4;
+}
+
 static void __init socfpga_map_io(void)
 {
 	socfpga_scu_map_io();
@@ -82,6 +93,11 @@ static void __init gic_init_irq(void)
 {
 	of_irq_init(irq_match);
 	socfpga_sysmgr_init();
+
+	if (of_machine_is_compatible("altr,socfpga-vt"))
+		init_socfpga_vt();
+	else
+		init_socfpga();
 }
 
 static void socfpga_cyclone5_restart(char mode, const char *cmd)
-- 
1.7.9.5

[PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware

[Pavel Machek]

Hi!


> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Because the CPU1 start address is different for socfpga-vt and
> socfpga-cyclone5, we add code to use the correct CPU1 start addr.
> 
> +++ b/arch/arm/configs/socfpga_defconfig
> @@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
>  # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
>  # CONFIG_CACHE_L2X0 is not set
>  CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_VMSPLIT_2G=y
>  CONFIG_SMP=y
>  CONFIG_NR_CPUS=2
>  CONFIG_AEABI=y

Is this related to CPU1 start address?

> +++ b/arch/arm/mach-socfpga/headsmp.S
> @@ -13,13 +13,19 @@
>  	__CPUINIT
>  	.arch	armv7-a
>  
> -#define CPU1_START_ADDR 	        0xffd08010
> -
>  ENTRY(secondary_trampoline)
> -	movw	r0, #:lower16:CPU1_START_ADDR
> -	movt  r0, #:upper16:CPU1_START_ADDR
> +	movw	r2, #:lower16:cpu1start_addr
> +	movt  r2, #:upper16:cpu1start_addr
>  
> +	ldr	r0, [r2]
>  	ldr	r1, [r0]
>  	bx	r1
>  
>  ENTRY(secondary_trampoline_end)
> +
> +#ifdef CONFIG_SMP
> +ENTRY(v7_secondary_startup)
> +       bl      v7_invalidate_l1
> +       b       secondary_startup
> +ENDPROC(v7_secondary_startup)
> +#endif

#ifdef should not be neccessary, as headsmp.S is only compiled when CONFIG_SMP. 

> +++ b/arch/arm/mach-socfpga/platsmp.c
> @@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
>  
>  	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
>  
> -	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
> +	__raw_writel(virt_to_phys(v7_secondary_startup),
> +		(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
>  

The math is rather interesting here; is (sys_manager_base_addr +
(cpu1start_addr & 0x000000ff)) == cpu1start_addr ?

> @@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
>  	iotable_init(&scu_io_desc, 1);
>  }
>  
> +static void __init init_socfpga_vt(void)
> +{
> +	cpu1start_addr = 0xffd08010;
> +}
> +
> +static void __init init_socfpga(void)
> +{
> +	cpu1start_addr = 0xffd080c4;
> +}

Should this be put into device tree somewhere?

In addition, this patch seems to break operation in the emulator for
me. In fact, it looks pretty much like emulator crash, with continuous
scroll of

B_TRANSPORT::(R(Addr=0x23092FD0, Count=08 ...

[sorry, it is hard to copy moving messages].

I'm using kernel based on 3.7-rc2. Should I attempt updating?

Thanks,
									Pavel 
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware

[Dinh Nguyen]

Hi Pavel,

On Fri, 2013-01-25 at 18:55 +0100, Pavel Machek wrote:
> Hi!
> 
> 
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Because the CPU1 start address is different for socfpga-vt and
> > socfpga-cyclone5, we add code to use the correct CPU1 start addr.
> > 
> > +++ b/arch/arm/configs/socfpga_defconfig
> > @@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
> >  # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
> >  # CONFIG_CACHE_L2X0 is not set
> >  CONFIG_HIGH_RES_TIMERS=y
> > +CONFIG_VMSPLIT_2G=y
> >  CONFIG_SMP=y
> >  CONFIG_NR_CPUS=2
> >  CONFIG_AEABI=y
> 
> Is this related to CPU1 start address?

Yes, it's really only necessary when running the virtual simulator.

> 
> > +++ b/arch/arm/mach-socfpga/headsmp.S
> > @@ -13,13 +13,19 @@
> >  	__CPUINIT
> >  	.arch	armv7-a
> >  
> > -#define CPU1_START_ADDR 	        0xffd08010
> > -
> >  ENTRY(secondary_trampoline)
> > -	movw	r0, #:lower16:CPU1_START_ADDR
> > -	movt  r0, #:upper16:CPU1_START_ADDR
> > +	movw	r2, #:lower16:cpu1start_addr
> > +	movt  r2, #:upper16:cpu1start_addr
> >  
> > +	ldr	r0, [r2]
> >  	ldr	r1, [r0]
> >  	bx	r1
> >  
> >  ENTRY(secondary_trampoline_end)
> > +
> > +#ifdef CONFIG_SMP
> > +ENTRY(v7_secondary_startup)
> > +       bl      v7_invalidate_l1
> > +       b       secondary_startup
> > +ENDPROC(v7_secondary_startup)
> > +#endif
> 
> #ifdef should not be neccessary, as headsmp.S is only compiled when CONFIG_SMP. 
> 
> > +++ b/arch/arm/mach-socfpga/platsmp.c
> > @@ -49,7 +49,8 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct
> >  
> >  	memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
> >  
> > -	__raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
> > +	__raw_writel(virt_to_phys(v7_secondary_startup),
> > +		(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
> >  
> 
> The math is rather interesting here; is (sys_manager_base_addr +
> (cpu1start_addr & 0x000000ff)) == cpu1start_addr ?
> 
> > @@ -55,6 +56,16 @@ static void __init socfpga_scu_map_io(void)
> >  	iotable_init(&scu_io_desc, 1);
> >  }
> >  
> > +static void __init init_socfpga_vt(void)
> > +{
> > +	cpu1start_addr = 0xffd08010;
> > +}
> > +
> > +static void __init init_socfpga(void)
> > +{
> > +	cpu1start_addr = 0xffd080c4;
> > +}
> 
> Should this be put into device tree somewhere?
> 
> In addition, this patch seems to break operation in the emulator for
> me. In fact, it looks pretty much like emulator crash, with continuous
> scroll of
> 
> B_TRANSPORT::(R(Addr=0x23092FD0, Count=08 ...

Definitely make sure CONFIG_VMSPLIT_2G=y is set for the Virtual Target.

Dinh
> 
> [sorry, it is hard to copy moving messages].
> 
> I'm using kernel based on 3.7-rc2. Should I attempt updating?
> 
> Thanks,
> 									Pavel 

[PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware

[Pavel Machek]

Hi!

> > > Because the CPU1 start address is different for socfpga-vt and
> > > socfpga-cyclone5, we add code to use the correct CPU1 start addr.
> > > 
> > > +++ b/arch/arm/configs/socfpga_defconfig
> > > @@ -21,6 +21,7 @@ CONFIG_ARM_THUMBEE=y
> > >  # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
> > >  # CONFIG_CACHE_L2X0 is not set
> > >  CONFIG_HIGH_RES_TIMERS=y
> > > +CONFIG_VMSPLIT_2G=y
> > >  CONFIG_SMP=y
> > >  CONFIG_NR_CPUS=2
> > >  CONFIG_AEABI=y
> > 
> > Is this related to CPU1 start address?
> 
> Yes, it's really only necessary when running the virtual simulator.

Aha, but defconfig does not mean that people will not try that
config (and it may be useful for multiarch kernels etc). If we don't
know what the cause is, what about this?

Remove unneccessary #ifdef.

socfpga will not boot in VMSPLIT_3G mode on emulator for some
reason. Warn when such configuration is detected, and fall back to UP
mode (so that user has chance to read the message).

Thanks,
								Pavel

Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 44cd055..dabf325 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -23,9 +23,7 @@ ENTRY(secondary_trampoline)
 
 ENTRY(secondary_trampoline_end)
 
-#ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
        bl      v7_invalidate_l1
        b       secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index d54647e..81e0da0 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -75,6 +75,13 @@ static void __init socfpga_smp_init_cpus(void)
 
 	ncores = scu_get_core_count(socfpga_scu_base_addr);
 
+#ifndef CONFIG_VMSPLIT_2G
+	if (of_machine_is_compatible("altr,socfpga-vt")) {
+		printk("Emulator needs VMSPLIT_2G to work in SMP mode.\n");
+		early_printk("Emulator needs VMSPLIT_2G to work in SMP mode.\n");
+		ncores = 1;
+	}
+#endif
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
 

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware

[Pavel Machek]

Hi!

I believe cpu1start_addr should go to the device tree, so that this
code is not neccessary. Proposed patch is below...

Thanks,
								Pavel

> +static void __init init_socfpga_vt(void)
> +{
> +	cpu1start_addr = 0xffd08010;
> +}
> +
> +static void __init init_socfpga(void)
> +{
> +	cpu1start_addr = 0xffd080c4;
> +}
> +
...
> +
> +	if (of_machine_is_compatible("altr,socfpga-vt"))
> +		init_socfpga_vt();
> +	else
> +		init_socfpga();

commit b0d651bb4deeb0d8d08969a47b77d3317cbbc0a2
Author: Pavel <pavel@ucw.cz>
Date:   Mon Jan 28 20:28:06 2013 +0100

    Fix whitespace in socfpga.dtsi.
    
    Move cpu1-start-addr variable to device tree, so that config code is
    not neccessary in kernel.
    
    Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 688729f..35d4bdc 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -180,13 +180,13 @@
 		};
 
 		rstmgr at ffd05000 {
-				compatible = "altr,rst-mgr";
-				reg = <0xffd05000 0x1000>;
-			};
+			compatible = "altr,rst-mgr";
+			reg = <0xffd05000 0x1000>;
+		};
 
 		sysmgr at ffd08000 {
-				compatible = "altr,sys-mgr";
-				reg = <0xffd08000 0x4000>;
-			};
+			compatible = "altr,sys-mgr";
+			reg = <0xffd08000 0x4000>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 1a6d088..e922475 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -56,5 +56,9 @@
 		serial1 at ffc03000 {
 			clock-frequency = <100000000>;
 		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd08010>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index df3551f..407ba14 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -56,5 +56,9 @@
 		serial1 at ffc03000 {
 			clock-frequency = <7372800>;
 		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd08010>;
+		};
 	};
 };
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 2d1e8db..bb17810 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -56,16 +56,6 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
-static void __init init_socfpga_vt(void)
-{
-	cpu1start_addr = 0xffd08010;
-}
-
-static void __init init_socfpga(void)
-{
-	cpu1start_addr = 0xffd080c4;
-}
-
 static void __init socfpga_map_io(void)
 {
 	socfpga_scu_map_io();
@@ -83,6 +73,11 @@ void __init socfpga_sysmgr_init(void)
 	struct device_node *np;
 
 	np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+
+	if (of_property_read_u32(np, "cpu1-start-addr", (u32 *) &cpu1start_addr)) {
+		early_printk("Need cpu1-start-addr in device tree.\n");
+		panic("Need cpu1-start-addr in device tree.\n");
+	}
 	sys_manager_base_addr = of_iomap(np, 0);
 
 	np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
@@ -93,11 +88,6 @@ static void __init gic_init_irq(void)
 {
 	of_irq_init(irq_match);
 	socfpga_sysmgr_init();
-
-	if (of_machine_is_compatible("altr,socfpga-vt"))
-		init_socfpga_vt();
-	else
-		init_socfpga();
 }
 
 static void socfpga_cyclone5_restart(char mode, const char *cmd)


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[RFC] socfpga: make function static

[Pavel Machek]

Hi!

While moving cpu1 start address into device tree, I noticed that
sysmgr_init can be static. Trivial patch is below.

Signed-off-by: Pavel Machek <pavel@denx.de>

commit 11030de41d7da7a14ca0c77abb726d6eec3a2fb7

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 323c74a..3ebd469 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -26,7 +26,6 @@ extern void v7_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
-extern void socfpga_sysmgr_init(void);
 
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index bb17810..334c330 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -68,7 +68,7 @@ const static struct of_device_id irq_match[] = {
 	{}
 };
 
-void __init socfpga_sysmgr_init(void)
+static void __init socfpga_sysmgr_init(void)
 {
 	struct device_node *np;
 
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv1 for soc 5/5] arm: socfpga: Add SMP support for actual socfpga harware

[Pavel Machek]

Hi!

> index 9941caa..5b76dd4 100644
> --- a/arch/arm/mach-socfpga/core.h
> +++ b/arch/arm/mach-socfpga/core.h
> @@ -20,7 +20,7 @@
>  #ifndef __MACH_CORE_H
>  #define __MACH_CORE_H
>  
> -extern void secondary_startup(void);
> +extern void v7_secondary_startup(void);
>  extern void __iomem *socfpga_scu_base_addr;
>  

One more thing. v7_secondary_startup() may be too generic name for a
symbol. mach-imx already uses that.

Plus, mach-imx also has the useless #ifdef.

---

Remove useless #ifdef; headsmp.S is only compiled in CONFIG_SMP
configuration.

Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb..4c9ec06 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -64,12 +64,10 @@ ENTRY(v7_invalidate_l1)
 	mov	pc, lr
 ENDPROC(v7_invalidate_l1)
 
-#ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
 	bl	v7_invalidate_l1
 	b	secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
 
 #ifdef CONFIG_PM
 /*


Thanks,
									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html