Re: [PATCH] MIPS: add irqdomain support for the CPU IRQ controller

[John Crispin <john@phrozen.org>]

> Is it necessary to use the word 'intc'? What does that mean? Perhaps
> "mti,cpu-interrupt-controller"?
>

the name is only a detail and if you prefer said name i have no prolem 
with that.


>> Please use this as an actual device tree documentation binding.
>
> Yes, bindings should be documented in
> Documentation/devicetree/bindings/mips

Sure i will repost in a bit with a binding document

> Just to satisfy my curiosity, Which drivers are using (or will be using)
> these mapping facilities? The timer and performance counters already
> work, so it isn't needed for them. What will use this.

we updated the ralink series i posted a few days ago to make use of this 
patch.

the SoC has its own irq controller behind STATUSF_IP2.

STATUSF_IP5 is wired to ethernet and STATUSF_IP6 is wired to wifi

i think on some socs from ralink the pci is wired to STATUSF_IP3

to be able to nicely represent this in a devicetree we need an entry for 
the mips cpu interrupt controller.

as the patch no exists I am considering to update the lantiq code to 
make use of it. Also the patch originates from gabors ath79 devicetree 
series, which also makes use of it.

	John