diff for duplicates of <510F5518.1010307@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index ee89d2b..529052f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,12 +2,12 @@ On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote: > Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. > Introduce a table based approach and switch PLLU to it. > -> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> > --- Looks good to me. -Reviewed-by: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> > drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------ > drivers/clk/tegra/clk-tegra20.c | 7 +++++++ diff --git a/a/content_digest b/N1/content_digest index bf494d4..62bdf54 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,35 +1,21 @@ "ref\01359713962-16822-1-git-send-email-pdeschrijver@nvidia.com\0" "ref\01359713962-16822-4-git-send-email-pdeschrijver@nvidia.com\0" - "ref\01359713962-16822-4-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" - "From\0Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Subject\0Re: [PATCH v5 03/10] clk: tegra: Add PLL post divider table\0" + "From\0pgaikwad@nvidia.com (Prashant Gaikwad)\0" + "Subject\0[PATCH v5 03/10] clk: tegra: Add PLL post divider table\0" "Date\0Mon, 4 Feb 2013 11:58:40 +0530\0" - "To\0Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>" - Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org> - Rob Landley <rob-VoJi6FS/r0vR7s880joybQ@public.gmane.org> - Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> - Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> - Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> - Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org <devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org> - linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:\n" "> Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.\n" "> Introduce a table based approach and switch PLLU to it.\n" ">\n" - "> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>\n" "> ---\n" "\n" "Looks good to me.\n" "\n" - "Reviewed-by: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>\n" "\n" "> drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------\n" "> drivers/clk/tegra/clk-tegra20.c | 7 +++++++\n" @@ -200,4 +186,4 @@ "> /**\n" > -5350cc139909edd252c07fbecfb0977e7c3700296bb6c3895c02dee0dad368b6 +a9f8fda56f6e4d7a6fe7f51cb58728ed5c42570045ac7f65ba3176cbb82e9bb8
diff --git a/a/1.txt b/N2/1.txt index ee89d2b..529052f 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -2,12 +2,12 @@ On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote: > Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. > Introduce a table based approach and switch PLLU to it. > -> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> > --- Looks good to me. -Reviewed-by: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> > drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------ > drivers/clk/tegra/clk-tegra20.c | 7 +++++++ diff --git a/a/content_digest b/N2/content_digest index bf494d4..70ca653 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,35 +1,34 @@ "ref\01359713962-16822-1-git-send-email-pdeschrijver@nvidia.com\0" "ref\01359713962-16822-4-git-send-email-pdeschrijver@nvidia.com\0" - "ref\01359713962-16822-4-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" - "From\0Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0Prashant Gaikwad <pgaikwad@nvidia.com>\0" "Subject\0Re: [PATCH v5 03/10] clk: tegra: Add PLL post divider table\0" "Date\0Mon, 4 Feb 2013 11:58:40 +0530\0" - "To\0Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Cc\0Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>" - Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org> - Rob Landley <rob-VoJi6FS/r0vR7s880joybQ@public.gmane.org> - Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> - Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> - Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> - Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org <devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org> - linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "To\0Peter De Schrijver <pdeschrijver@nvidia.com>\0" + "Cc\0Grant Likely <grant.likely@secretlab.ca>" + Rob Herring <rob.herring@calxeda.com> + Rob Landley <rob@landley.net> + Stephen Warren <swarren@wwwdotorg.org> + Russell King <linux@arm.linux.org.uk> + Simon Glass <sjg@chromium.org> + Mike Turquette <mturquette@linaro.org> + Joseph Lo <josephl@nvidia.com> + devicetree-discuss@lists.ozlabs.org <devicetree-discuss@lists.ozlabs.org> + linux-doc@vger.kernel.org <linux-doc@vger.kernel.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" "\00:1\0" "b\0" "On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:\n" "> Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.\n" "> Introduce a table based approach and switch PLLU to it.\n" ">\n" - "> Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>\n" "> ---\n" "\n" "Looks good to me.\n" "\n" - "Reviewed-by: Prashant Gaikwad <pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>\n" "\n" "> drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------\n" "> drivers/clk/tegra/clk-tegra20.c | 7 +++++++\n" @@ -200,4 +199,4 @@ "> /**\n" > -5350cc139909edd252c07fbecfb0977e7c3700296bb6c3895c02dee0dad368b6 +15a38cfe8352c9efa9eb811b343e21c6a80ffbf81de0f27d8eb85f1b2361a474
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