From mboxrd@z Thu Jan 1 00:00:00 1970 From: Prashant Gaikwad Subject: Re: [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114 Date: Mon, 4 Feb 2013 12:05:29 +0530 Message-ID: <510F56B1.5060409@nvidia.com> References: <1359713962-16822-1-git-send-email-pdeschrijver@nvidia.com> <1359713962-16822-5-git-send-email-pdeschrijver@nvidia.com> <510C1A2E.5010408@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <510C1A2E.5010408-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rhyland Klein Cc: Peter De Schrijver , Grant Likely , Rob Herring , Rob Landley , Stephen Warren , Russell King , Simon Glass , Mike Turquette , Joseph Lo , "devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" , "linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: linux-tegra@vger.kernel.org On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote: > On 2/1/2013 5:18 AM, Peter De Schrijver wrote: >> Tegra114 introduces new PLL types. This requires new clocktypes as well >> as some new fields in the pll structure. >> >> Signed-off-by: Peter De Schrijver >> --- >> drivers/clk/tegra/clk-pll.c | 719 +++++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/tegra/clk.h | 47 +++ >> 2 files changed, 766 insertions(+), 0 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c >> index 87d2f34..50114b7 100644 >> --- a/drivers/clk/tegra/clk-pll.c >> +++ b/drivers/clk/tegra/clk-pll.c >> [snip] >> +struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, >> + void __iomem *clk_base, void __iomem *pmc, >> + unsigned long flags, unsigned long fixed_rate, >> + struct tegra_clk_pll_params *pll_params, >> + u32 pll_flags, >> + struct tegra_clk_pll_freq_table *freq_table, >> + spinlock_t *lock) >> +{ >> + if (!pll_params->pdiv_tohw) >> + return -EINVAL; >> + > This will cause the following warning: > warning: return makes pointer from integer without a cast > > Same with occurrences in tegra_clk_register_pllm and > tegra_clk_register_pllc. > > Should this instead be returning NULL? return ERR_PTR(-EINVAL) > > -rhyland > From mboxrd@z Thu Jan 1 00:00:00 1970 From: pgaikwad@nvidia.com (Prashant Gaikwad) Date: Mon, 4 Feb 2013 12:05:29 +0530 Subject: [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114 In-Reply-To: <510C1A2E.5010408@nvidia.com> References: <1359713962-16822-1-git-send-email-pdeschrijver@nvidia.com> <1359713962-16822-5-git-send-email-pdeschrijver@nvidia.com> <510C1A2E.5010408@nvidia.com> Message-ID: <510F56B1.5060409@nvidia.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote: > On 2/1/2013 5:18 AM, Peter De Schrijver wrote: >> Tegra114 introduces new PLL types. This requires new clocktypes as well >> as some new fields in the pll structure. >> >> Signed-off-by: Peter De Schrijver >> --- >> drivers/clk/tegra/clk-pll.c | 719 +++++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/tegra/clk.h | 47 +++ >> 2 files changed, 766 insertions(+), 0 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c >> index 87d2f34..50114b7 100644 >> --- a/drivers/clk/tegra/clk-pll.c >> +++ b/drivers/clk/tegra/clk-pll.c >> [snip] >> +struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, >> + void __iomem *clk_base, void __iomem *pmc, >> + unsigned long flags, unsigned long fixed_rate, >> + struct tegra_clk_pll_params *pll_params, >> + u32 pll_flags, >> + struct tegra_clk_pll_freq_table *freq_table, >> + spinlock_t *lock) >> +{ >> + if (!pll_params->pdiv_tohw) >> + return -EINVAL; >> + > This will cause the following warning: > warning: return makes pointer from integer without a cast > > Same with occurrences in tegra_clk_register_pllm and > tegra_clk_register_pllc. > > Should this instead be returning NULL? return ERR_PTR(-EINVAL) > > -rhyland > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752746Ab3BDGfq (ORCPT ); Mon, 4 Feb 2013 01:35:46 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:5917 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751632Ab3BDGfo (ORCPT ); Mon, 4 Feb 2013 01:35:44 -0500 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Sun, 03 Feb 2013 22:35:37 -0800 Message-ID: <510F56B1.5060409@nvidia.com> Date: Mon, 4 Feb 2013 12:05:29 +0530 From: Prashant Gaikwad User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121011 Thunderbird/16.0.1 MIME-Version: 1.0 To: Rhyland Klein CC: Peter De Schrijver , Grant Likely , Rob Herring , Rob Landley , Stephen Warren , Russell King , Simon Glass , Mike Turquette , Joseph Lo , "devicetree-discuss@lists.ozlabs.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114 References: <1359713962-16822-1-git-send-email-pdeschrijver@nvidia.com> <1359713962-16822-5-git-send-email-pdeschrijver@nvidia.com> <510C1A2E.5010408@nvidia.com> In-Reply-To: <510C1A2E.5010408@nvidia.com> X-NVConfidentiality: public Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote: > On 2/1/2013 5:18 AM, Peter De Schrijver wrote: >> Tegra114 introduces new PLL types. This requires new clocktypes as well >> as some new fields in the pll structure. >> >> Signed-off-by: Peter De Schrijver >> --- >> drivers/clk/tegra/clk-pll.c | 719 +++++++++++++++++++++++++++++++++++++++++++ >> drivers/clk/tegra/clk.h | 47 +++ >> 2 files changed, 766 insertions(+), 0 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c >> index 87d2f34..50114b7 100644 >> --- a/drivers/clk/tegra/clk-pll.c >> +++ b/drivers/clk/tegra/clk-pll.c >> [snip] >> +struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, >> + void __iomem *clk_base, void __iomem *pmc, >> + unsigned long flags, unsigned long fixed_rate, >> + struct tegra_clk_pll_params *pll_params, >> + u32 pll_flags, >> + struct tegra_clk_pll_freq_table *freq_table, >> + spinlock_t *lock) >> +{ >> + if (!pll_params->pdiv_tohw) >> + return -EINVAL; >> + > This will cause the following warning: > warning: return makes pointer from integer without a cast > > Same with occurrences in tegra_clk_register_pllm and > tegra_clk_register_pllc. > > Should this instead be returning NULL? return ERR_PTR(-EINVAL) > > -rhyland >