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To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com References: <20260520160728.2283628-1-rathc@linux.ibm.com> <20260520160728.2283628-14-rathc@linux.ibm.com> Content-Language: en-US From: Nikhil Kumar Singh In-Reply-To: <20260520160728.2283628-14-rathc@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: S7csifuL8yDcaeGHlGQKzUXxbjj1PmiU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDA0MyBTYWx0ZWRfX3OzHXojzXuKe drkeN8Kg6l3Uu2GNtTCEJz+QRwEdZReiWNgCsozGeaJxIzthKmhNR+u91Ai3H5L77OIz/14ZXHa ZYMT9qaxwXD6P5H9xtX6oD5wWlPQjS9M4r1CQMjz8TQI6/fE6aneBWe0djr+WPjHR7kU57dKr5u 1cuGVjmQ8rMUKvc5uWSGDDLfmpEtcViS26Ps4nMsoHeoFT9NzLUMje7wU+e9/4XzyDdJZqpX9BO IlyJqCAsHC34WOXCmBoykKKW331OqavQkr2Imbzz553uAzKd3bBUL1ejF5idL4R71dHI5Foa7j8 EBMASs4hFOI4NFIt1Pl7Hgn49Jd21IxY7GhsuVP5TGaRtocZgoQ+e4ZwYLo4mMBzf7lgDutzOIJ vxehJdOaVSZxYDKBGr3UYqc+8CgJRHWKa4v4f/jcowdJuolrFZ8R7fOJ7Bt4eIqo2UiGlgjoVSN 9MKCJhFhk4avDFpkkRw== X-Proofpoint-ORIG-GUID: CUjMbgdiGnUE1eUOqOZ_sHGlWlbVRgB5 X-Authority-Analysis: v=2.4 cv=FqQ1OWrq c=1 sm=1 tr=0 ts=6a4c8743 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=gIVu_BG64Y15aQVwIEYA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDA0MyBTYWx0ZWRfX+8kKByVPO3mL qFz/BrqyqsfIdNRsSF3UqAq7+yqWh3De4dFCvhkt/7QuVlGLGw9GDGKNyise9Pq0B4HuR71iaO7 sTN/1x1utS58y9wkRxxErpWmptQhEQs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_01,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070043 Received-SPF: pass client-ip=148.163.156.1; envelope-from=nikhilks@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Nikhil Kumar Singh Thanks, ~ Nikhil On 20/05/26 21:37, Chinmay Rath wrote: > From: Ojaswin Mujoo > > Moving the following instructions to decodetree specification : > isync > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the '-d > in_asm,op' flag. > > Signed-off-by: Ojaswin Mujoo > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 1 + > target/ppc/translate.c | 15 --------------- > target/ppc/translate/storage-ctrl-impl.c.inc | 17 +++++++++++++++++ > 3 files changed, 18 insertions(+), 15 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index f35f7113a0..cbb7a2ed51 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -1462,6 +1462,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - > @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync > SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync > EIEIO 011111 ----- ----- ----- 1101010110 - > +ISYNC 010011 ----- ----- ----- 0010010110 - > > # Condition Register Field Instruction > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 2345bf8867..770f52e7d4 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) > static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } > #endif > > -/* isync */ > -static void gen_isync(DisasContext *ctx) > -{ > - /* > - * We need to check for a pending TLB flush. This can only happen in > - * kernel mode however so check MSR_PR > - */ > - if (!ctx->pr) { > - gen_check_tlb_flush(ctx, false); > - } > - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > - ctx->base.is_jmp = DISAS_EXIT_UPDATE; > -} > - > /* wait */ > static void gen_wait(DisasContext *ctx) > { > @@ -5401,7 +5387,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), > GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), > GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), > GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), > -GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), > /* ISA v3.0 changed the extended opcode from 62 to 30 */ > GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), > GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), > diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc > index b8b4454663..943229c438 100644 > --- a/target/ppc/translate/storage-ctrl-impl.c.inc > +++ b/target/ppc/translate/storage-ctrl-impl.c.inc > @@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a) > return true; > } > > +static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a) > +{ > + REQUIRE_INSNS_FLAGS(ctx, MEM); > + > + /* > + * We need to check for a pending TLB flush. This can only happen in > + * kernel mode however so check MSR_PR > + */ > + if (!ctx->pr) { > + gen_check_tlb_flush(ctx, false); > + } > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > + ctx->base.is_jmp = DISAS_EXIT_UPDATE; > + > + return true; > +} > + > static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) > { > REQUIRE_64BIT(ctx);