[U-Boot] [PATCH v3] mx6: Disable Power Down Bit of watchdog

[Stefano Babic <sbabic@denx.de>]

On 07/02/2013 17:45, Fabio Estevam wrote:
> On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted 
> and it is not able to reach the Linux prompt.
> 
> Comparing the watchdog behaviour on a revB versus revC board:
> 
> - On a mx6qsabresd revB:
> 
> U-Boot > reset
> resetting ...
> 
> U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
> 
> CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
> Reset cause: WDOG
> ...
> 
> - On a mx6qsabresd revC:
> 
> U-Boot > reset
> resetting ...
> 
> U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
> 
> CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
> Reset cause: POR
> 
> So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.
> 
> Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
> is also safe for all mx6 boards.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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