From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UBO1V-00074G-8d for qemu-devel@nongnu.org; Fri, 01 Mar 2013 06:21:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UBO1P-0001Lm-Sb for qemu-devel@nongnu.org; Fri, 01 Mar 2013 06:21:09 -0500 Received: from mel.act-europe.fr ([194.98.77.210]:50636) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UBO1P-0001Lg-IE for qemu-devel@nongnu.org; Fri, 01 Mar 2013 06:21:03 -0500 Message-ID: <51308F1D.1080600@adacore.com> Date: Fri, 01 Mar 2013 12:21:01 +0100 From: Fabien Chouteau MIME-Version: 1.0 References: <512E3637.6070609@adacore.com> <512E4170.4070003@adacore.com> <201302272049.59409.paul@codesourcery.com> <512F6336.6090206@adacore.com> <512F965B.1000007@adacore.com> <51307F46.4080606@adacore.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [ARM] Cortex-R4F and VFP3-D16 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paul Brook , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , "qemu-devel@nongnu.org" On 03/01/2013 11:40 AM, Peter Maydell wrote: > On 1 March 2013 10:13, Fabien Chouteau wrote: >> On 02/28/2013 07:42 PM, Peter Maydell wrote: >>> How are you handling the SCTLR IE and EE bits? >> >> I did nothing, as far as I know it's not possible to switch endianness >> in QEMU. > > Yes, that's why I'm wondering how you're handling them. > >> TMS570 are configured for big-endian only, so this is not a >> problem for me. > > Do you mean they are BE8 for load/stores always (ie SCTLR.EE is > 1, or that they are both BE8 for load/stores and also for > instruction fetches (ie that SCTLR.IE is also 1) ? > > Endianness in ARM is not as simple as a single flag saying > "big or little"... > I'm new to this ARM architecture so I will just quote the doc. TMS570LS31x/21x Technical Reference Manual: "The TMS570 family is based on the ARM=C2=AE CortexTM-R4F core. ARM has designed this core to be used in big-endian and little-endian systems. For the TI TMS570 family, the endianness has been configured to BE32." >>>>> Are you planning to do the v7 PMSA support? >>> >>>> I don't know what that is, but I'll take a look :) >>> >>> It's the Memory Protection Unit -- QEMU currently only has the >>> old v5 MPU, and register_cpu_regs_for_features() will assert >>> if your CPU is v6 or v7 and has the FEATURE_MPU bit set. >>> If you're putting in system emulation for an R4 then you must >>> implement this (and I'm surprised you've managed to get anything >>> significant to run without it). >> >> The programs I run don't need MPU, so for the moment I have no plan to >> implement PMSA. > > However from an upstream point of view something that claims > to be an R4 but doesn't actually implement the MPU is not > terribly useful... > Well it is useful for us. Our safety-critical small-foot-print run-time doesn't need MPU. Look for Ravenscar profile in Ada. Regards, --=20 Fabien Chouteau