From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23064CD4F54 for ; Fri, 29 May 2026 18:19:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63CF41123B0; Fri, 29 May 2026 18:19:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; secure) header.d=sntech.de header.i=@sntech.de header.b="iudeHZxJ"; dkim-atps=neutral Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9DCCD1123B0 for ; Fri, 29 May 2026 18:19:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=MezAljbMtu/a/IWnbTDAtFD/p1r8DFJmzsXD7QfO5sE=; b=iudeHZxJStlryOmQAUHhsleY6G 6XU21yner9VdSVJz2LnIP66KoBRM3GZ3FMalVNbytmY4chArURs0O4Um31YsLhxSP9UTyIuvArUnr pBGSlvQyxFlIV9a7MRAPChCJ6sewkACEUUtK80hGptBuDlq5bOXMgBph63rx5Y/70Pg9cClKVjBbe alBOV5l6R8Yivt0+ULO6bzAQiwKRScSZ1Po2AjcaSpWhJKxpkZV6B974c8sCnfmy1R5ppPEgk+xjg 2/2M59Qq6ylmGuu8I5GcIDs/cUXizKa+cYPYXKQ+yGa3OJYrwUYgV9u0OuW8Q/aC+PgkFYeKPlDNb H3E2FJjw==; From: Heiko Stuebner To: Tomeu Vizoso , Oded Gabbay , MidG971 Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: Re: [PATCH v2 1/4] accel: rocket: Add support for Rockchip RK3568 Date: Fri, 29 May 2026 20:19:50 +0200 Message-ID: <5132269.NnENhoQgcM@phil> In-Reply-To: <20260529155824.3099831-2-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> <20260529155824.3099831-2-midgy971@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Am Freitag, 29. Mai 2026, 17:58:21 Mitteleurop=C3=A4ische Sommerzeit schrie= b MidG971: > From: Midgy BALON >=20 > The RK3568 has a single NVDLA-derived NPU core (0.8 TOPS), the same IP > family as the three-core RK3588 NPU already supported by the Rocket > driver. To accommodate both SoCs: >=20 > - Introduce a per-SoC rocket_soc_data structure carrying dma_bits and > an optional noc_init callback, plumbed through of_device_get_match_data(). > - rocket_device_init() now scans for both rk3568 and rk3588 RKNN cores > and picks the narrower DMA width (32-bit) when an RK3568 core is present. > - Add rk3568_soc_data and rk3568_noc_init() handling the three RK3568- > specific initialisation steps that must run after the power domain is > on and clocks are enabled: if you need bullet points to describe your patch, that strongly indicates these need to be multple patches. I.e. the move of the relevant parts to a per-soc data is one patch (and only having the rk3588 soc-data in that one). >=20 > 1. PVTPLL initialisation: The NPU uses a PVTPLL ring oscillator > managed by TF-A via SCMI for rates above 400 MHz. A two-step > clk_set_rate() sequence (600 MHz then 1 GHz) forces two SCMI calls > to TF-A even if the kernel clock framework would skip an unchanged > rate. The PVTPLL must be running before the NPU NOC bus will > acknowledge a de-idle request. >=20 > 2. Explicit NPU power-on (PWR_GATE_SFTCON): The RK3568_PD_NPU power > domain is marked always_on in pm-domains.c, so the generic power > domain framework power_on() callback is a no-op. The NPU hardware > can remain power-gated at boot. Writing bit 1 =3D 0 to PWR_GATE_SFTCON > (PMU offset 0xa0) explicitly powers on the NPU hardware before the > de-idle request is issued. >=20 > 3. NOC bus de-idle: Disable NPU NOC auto-idle (NOC_AUTO_CON0 bit 2), > request de-idle (BUS_IDLE_SFTCON0 bit 2 =3D 0), then poll > BUS_IDLE_ST (PMU offset 0x60) until bit 2 clears (bus active). >=20 > The RK3568 DMA address space is limited to 32 bits, as the NPU AXI bus > and IOMMU page walker cannot address memory above 4 GB. >=20 > All PMU accesses follow the RK3568 write-mask protocol: upper 16 bits are > the write-enable mask for the lower 16 bits. >=20 > Signed-off-by: Midgy BALON [...] > diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/= rocket_device.c > index 46e6ee1e7..0ed8251c8 100644 > --- a/drivers/accel/rocket/rocket_device.c > +++ b/drivers/accel/rocket/rocket_device.c > @@ -27,6 +27,9 @@ struct rocket_device *rocket_device_init(struct platfor= m_device *pdev, > ddev =3D &rdev->ddev; > dev_set_drvdata(dev, rdev); > =20 > + for_each_compatible_node(core_node, NULL, "rockchip,rk3568-rknn-core") > + if (of_device_is_available(core_node)) > + num_cores++; > for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core") > if (of_device_is_available(core_node)) > num_cores++; > @@ -37,9 +40,25 @@ struct rocket_device *rocket_device_init(struct platfo= rm_device *pdev, > =20 > dma_set_max_seg_size(dev, UINT_MAX); > =20 > - err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); > - if (err) > - return ERR_PTR(err); for both changes in rocket_device_init(): rocket_device_init() gets called from the main probe function, so before calling rocket_device_init() you can already access the specific soc data from the compatible and can derive both that for_each above, and the dma- width, directly from that. No need for that loop below. > + /* Use the DMA width of the first available RKNN core. RK3568 cores > + * are 32-bit; RK3588 are 40-bit. If both are present we pick the > + * narrower mask. > + */ > + { > + struct device_node *n; > + unsigned int dma_bits =3D 40; > + > + for_each_compatible_node(n, NULL, "rockchip,rk3568-rknn-core") > + if (of_device_is_available(n)) { > + dma_bits =3D 32; > + of_node_put(n); > + break; > + } > + > + err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_bits)); > + if (err) > + return ERR_PTR(err); > + } Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 533ADCD4F54 for ; Fri, 29 May 2026 18:20:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5DUT7KJJRapB1gusqBdxGXbMyKJD8CjdvDcrkE8Jlw4=; b=CFpKHa/yRHeDYH gHgeqeBCyFqlP1qMF1QhMCnHpKRXsTToOcXvZAPaRMMUv5EXwXiOsESk/8YsIfmzTQj+rTV/YL8xs x3/HgTaJ4r7Qu9tWPwLmfCLBnuo+HU8nVgNEYvtQ/9ysqYWCnVb38Vyw9yRbeMP71W9ITmSd6OhCU K5+XqZ4o5y4lnhhnJ90IZL1lEfBLxaw56co8n2DKKcAhBKgDc4XqTUexc96b80dFej/xTIVRLz0+k k76oIWekFB184H8a5Z1n1PUTSN3CXlOrrA1fWZYA3iKlRmwincOSLvWmJgdHu6KWLoN2VOXzaLp9U VLdsyQeD9Q+It0+86+mg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wT1oM-000000085t2-2gk3; Fri, 29 May 2026 18:19:58 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wT1oJ-000000085s7-1rx8; Fri, 29 May 2026 18:19:56 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=MezAljbMtu/a/IWnbTDAtFD/p1r8DFJmzsXD7QfO5sE=; b=iudeHZxJStlryOmQAUHhsleY6G 6XU21yner9VdSVJz2LnIP66KoBRM3GZ3FMalVNbytmY4chArURs0O4Um31YsLhxSP9UTyIuvArUnr pBGSlvQyxFlIV9a7MRAPChCJ6sewkACEUUtK80hGptBuDlq5bOXMgBph63rx5Y/70Pg9cClKVjBbe alBOV5l6R8Yivt0+ULO6bzAQiwKRScSZ1Po2AjcaSpWhJKxpkZV6B974c8sCnfmy1R5ppPEgk+xjg 2/2M59Qq6ylmGuu8I5GcIDs/cUXizKa+cYPYXKQ+yGa3OJYrwUYgV9u0OuW8Q/aC+PgkFYeKPlDNb H3E2FJjw==; From: Heiko Stuebner To: Tomeu Vizoso , Oded Gabbay , MidG971 Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Midgy BALON Subject: Re: [PATCH v2 1/4] accel: rocket: Add support for Rockchip RK3568 Date: Fri, 29 May 2026 20:19:50 +0200 Message-ID: <5132269.NnENhoQgcM@phil> In-Reply-To: <20260529155824.3099831-2-midgy971@gmail.com> References: <20260529155824.3099831-1-midgy971@gmail.com> <20260529155824.3099831-2-midgy971@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260529_111955_483678_5EDC9493 X-CRM114-Status: GOOD ( 25.59 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org SGksCgpBbSBGcmVpdGFnLCAyOS4gTWFpIDIwMjYsIDE3OjU4OjIxIE1pdHRlbGV1cm9ww6Rpc2No ZSBTb21tZXJ6ZWl0IHNjaHJpZWIgTWlkRzk3MToKPiBGcm9tOiBNaWRneSBCQUxPTiA8bWlkZ3k5 NzFAZ21haWwuY29tPgo+IAo+IFRoZSBSSzM1NjggaGFzIGEgc2luZ2xlIE5WRExBLWRlcml2ZWQg TlBVIGNvcmUgKDAuOCBUT1BTKSwgdGhlIHNhbWUgSVAKPiBmYW1pbHkgYXMgdGhlIHRocmVlLWNv cmUgUkszNTg4IE5QVSBhbHJlYWR5IHN1cHBvcnRlZCBieSB0aGUgUm9ja2V0Cj4gZHJpdmVyLiBU byBhY2NvbW1vZGF0ZSBib3RoIFNvQ3M6Cj4gCj4gICAtIEludHJvZHVjZSBhIHBlci1Tb0Mgcm9j a2V0X3NvY19kYXRhIHN0cnVjdHVyZSBjYXJyeWluZyBkbWFfYml0cyBhbmQKPiBhbiBvcHRpb25h bCBub2NfaW5pdCBjYWxsYmFjaywgcGx1bWJlZCB0aHJvdWdoIG9mX2RldmljZV9nZXRfbWF0Y2hf ZGF0YSgpLgo+ICAgLSByb2NrZXRfZGV2aWNlX2luaXQoKSBub3cgc2NhbnMgZm9yIGJvdGggcmsz NTY4IGFuZCByazM1ODggUktOTiBjb3Jlcwo+IGFuZCBwaWNrcyB0aGUgbmFycm93ZXIgRE1BIHdp ZHRoICgzMi1iaXQpIHdoZW4gYW4gUkszNTY4IGNvcmUgaXMgcHJlc2VudC4KPiAgIC0gQWRkIHJr MzU2OF9zb2NfZGF0YSBhbmQgcmszNTY4X25vY19pbml0KCkgaGFuZGxpbmcgdGhlIHRocmVlIFJL MzU2OC0KPiBzcGVjaWZpYyBpbml0aWFsaXNhdGlvbiBzdGVwcyB0aGF0IG11c3QgcnVuIGFmdGVy IHRoZSBwb3dlciBkb21haW4gaXMKPiBvbiBhbmQgY2xvY2tzIGFyZSBlbmFibGVkOgoKaWYgeW91 IG5lZWQgYnVsbGV0IHBvaW50cyB0byBkZXNjcmliZSB5b3VyIHBhdGNoLCB0aGF0IHN0cm9uZ2x5 IGluZGljYXRlcwp0aGVzZSBuZWVkIHRvIGJlIG11bHRwbGUgcGF0Y2hlcy4KSS5lLiB0aGUgbW92 ZSBvZiB0aGUgcmVsZXZhbnQgcGFydHMgdG8gYSBwZXItc29jIGRhdGEgaXMgb25lIHBhdGNoCihh bmQgb25seSBoYXZpbmcgdGhlIHJrMzU4OCBzb2MtZGF0YSBpbiB0aGF0IG9uZSkuCgoKCj4gCj4g MS4gUFZUUExMIGluaXRpYWxpc2F0aW9uOiBUaGUgTlBVIHVzZXMgYSBQVlRQTEwgcmluZyBvc2Np bGxhdG9yCj4gICAgbWFuYWdlZCBieSBURi1BIHZpYSBTQ01JIGZvciByYXRlcyBhYm92ZSA0MDAg TUh6LiBBIHR3by1zdGVwCj4gICAgY2xrX3NldF9yYXRlKCkgc2VxdWVuY2UgKDYwMCBNSHogdGhl biAxIEdIeikgZm9yY2VzIHR3byBTQ01JIGNhbGxzCj4gICAgdG8gVEYtQSBldmVuIGlmIHRoZSBr ZXJuZWwgY2xvY2sgZnJhbWV3b3JrIHdvdWxkIHNraXAgYW4gdW5jaGFuZ2VkCj4gICAgcmF0ZS4g VGhlIFBWVFBMTCBtdXN0IGJlIHJ1bm5pbmcgYmVmb3JlIHRoZSBOUFUgTk9DIGJ1cyB3aWxsCj4g ICAgYWNrbm93bGVkZ2UgYSBkZS1pZGxlIHJlcXVlc3QuCj4gCj4gMi4gRXhwbGljaXQgTlBVIHBv d2VyLW9uIChQV1JfR0FURV9TRlRDT04pOiBUaGUgUkszNTY4X1BEX05QVSBwb3dlcgo+ICAgIGRv bWFpbiBpcyBtYXJrZWQgYWx3YXlzX29uIGluIHBtLWRvbWFpbnMuYywgc28gdGhlIGdlbmVyaWMg cG93ZXIKPiAgICBkb21haW4gZnJhbWV3b3JrIHBvd2VyX29uKCkgY2FsbGJhY2sgaXMgYSBuby1v cC4gVGhlIE5QVSBoYXJkd2FyZQo+ICAgIGNhbiByZW1haW4gcG93ZXItZ2F0ZWQgYXQgYm9vdC4g V3JpdGluZyBiaXQgMSA9IDAgdG8gUFdSX0dBVEVfU0ZUQ09OCj4gICAgKFBNVSBvZmZzZXQgMHhh MCkgZXhwbGljaXRseSBwb3dlcnMgb24gdGhlIE5QVSBoYXJkd2FyZSBiZWZvcmUgdGhlCj4gICAg ZGUtaWRsZSByZXF1ZXN0IGlzIGlzc3VlZC4KPiAKPiAzLiBOT0MgYnVzIGRlLWlkbGU6IERpc2Fi bGUgTlBVIE5PQyBhdXRvLWlkbGUgKE5PQ19BVVRPX0NPTjAgYml0IDIpLAo+ICAgIHJlcXVlc3Qg ZGUtaWRsZSAoQlVTX0lETEVfU0ZUQ09OMCBiaXQgMiA9IDApLCB0aGVuIHBvbGwKPiAgICBCVVNf SURMRV9TVCAoUE1VIG9mZnNldCAweDYwKSB1bnRpbCBiaXQgMiBjbGVhcnMgKGJ1cyBhY3RpdmUp Lgo+IAo+IFRoZSBSSzM1NjggRE1BIGFkZHJlc3Mgc3BhY2UgaXMgbGltaXRlZCB0byAzMiBiaXRz LCBhcyB0aGUgTlBVIEFYSSBidXMKPiBhbmQgSU9NTVUgcGFnZSB3YWxrZXIgY2Fubm90IGFkZHJl c3MgbWVtb3J5IGFib3ZlIDQgR0IuCj4gCj4gQWxsIFBNVSBhY2Nlc3NlcyBmb2xsb3cgdGhlIFJL MzU2OCB3cml0ZS1tYXNrIHByb3RvY29sOiB1cHBlciAxNiBiaXRzIGFyZQo+IHRoZSB3cml0ZS1l bmFibGUgbWFzayBmb3IgdGhlIGxvd2VyIDE2IGJpdHMuCj4gCj4gU2lnbmVkLW9mZi1ieTogTWlk Z3kgQkFMT04gPG1pZGd5OTcxQGdtYWlsLmNvbT4KClsuLi5dCgo+IGRpZmYgLS1naXQgYS9kcml2 ZXJzL2FjY2VsL3JvY2tldC9yb2NrZXRfZGV2aWNlLmMgYi9kcml2ZXJzL2FjY2VsL3JvY2tldC9y b2NrZXRfZGV2aWNlLmMKPiBpbmRleCA0NmU2ZWUxZTcuLjBlZDgyNTFjOCAxMDA2NDQKPiAtLS0g YS9kcml2ZXJzL2FjY2VsL3JvY2tldC9yb2NrZXRfZGV2aWNlLmMKPiArKysgYi9kcml2ZXJzL2Fj Y2VsL3JvY2tldC9yb2NrZXRfZGV2aWNlLmMKPiBAQCAtMjcsNiArMjcsOSBAQCBzdHJ1Y3Qgcm9j a2V0X2RldmljZSAqcm9ja2V0X2RldmljZV9pbml0KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBk ZXYsCj4gIAlkZGV2ID0gJnJkZXYtPmRkZXY7Cj4gIAlkZXZfc2V0X2RydmRhdGEoZGV2LCByZGV2 KTsKPiAgCj4gKwlmb3JfZWFjaF9jb21wYXRpYmxlX25vZGUoY29yZV9ub2RlLCBOVUxMLCAicm9j a2NoaXAscmszNTY4LXJrbm4tY29yZSIpCj4gKwkJaWYgKG9mX2RldmljZV9pc19hdmFpbGFibGUo Y29yZV9ub2RlKSkKPiArCQkJbnVtX2NvcmVzKys7Cj4gIAlmb3JfZWFjaF9jb21wYXRpYmxlX25v ZGUoY29yZV9ub2RlLCBOVUxMLCAicm9ja2NoaXAscmszNTg4LXJrbm4tY29yZSIpCj4gIAkJaWYg KG9mX2RldmljZV9pc19hdmFpbGFibGUoY29yZV9ub2RlKSkKPiAgCQkJbnVtX2NvcmVzKys7Cj4g QEAgLTM3LDkgKzQwLDI1IEBAIHN0cnVjdCByb2NrZXRfZGV2aWNlICpyb2NrZXRfZGV2aWNlX2lu aXQoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldiwKPiAgCj4gIAlkbWFfc2V0X21heF9zZWdf c2l6ZShkZXYsIFVJTlRfTUFYKTsKPiAgCj4gLQllcnIgPSBkbWFfc2V0X21hc2tfYW5kX2NvaGVy ZW50KGRldiwgRE1BX0JJVF9NQVNLKDQwKSk7Cj4gLQlpZiAoZXJyKQo+IC0JCXJldHVybiBFUlJf UFRSKGVycik7Cgpmb3IgYm90aCBjaGFuZ2VzIGluIHJvY2tldF9kZXZpY2VfaW5pdCgpOgoKcm9j a2V0X2RldmljZV9pbml0KCkgZ2V0cyBjYWxsZWQgZnJvbSB0aGUgbWFpbiBwcm9iZSBmdW5jdGlv biwgc28gYmVmb3JlCmNhbGxpbmcgcm9ja2V0X2RldmljZV9pbml0KCkgeW91IGNhbiBhbHJlYWR5 IGFjY2VzcyB0aGUgc3BlY2lmaWMgc29jIGRhdGEKZnJvbSB0aGUgY29tcGF0aWJsZSBhbmQgY2Fu IGRlcml2ZSBib3RoIHRoYXQgZm9yX2VhY2ggYWJvdmUsIGFuZCB0aGUgZG1hLQp3aWR0aCwgZGly ZWN0bHkgZnJvbSB0aGF0LgoKTm8gbmVlZCBmb3IgdGhhdCBsb29wIGJlbG93LgoKPiArCS8qIFVz ZSB0aGUgRE1BIHdpZHRoIG9mIHRoZSBmaXJzdCBhdmFpbGFibGUgUktOTiBjb3JlLiAgUkszNTY4 IGNvcmVzCj4gKwkgKiBhcmUgMzItYml0OyBSSzM1ODggYXJlIDQwLWJpdC4gIElmIGJvdGggYXJl IHByZXNlbnQgd2UgcGljayB0aGUKPiArCSAqIG5hcnJvd2VyIG1hc2suCj4gKwkgKi8KPiArCXsK PiArCQlzdHJ1Y3QgZGV2aWNlX25vZGUgKm47Cj4gKwkJdW5zaWduZWQgaW50IGRtYV9iaXRzID0g NDA7Cj4gKwo+ICsJCWZvcl9lYWNoX2NvbXBhdGlibGVfbm9kZShuLCBOVUxMLCAicm9ja2NoaXAs cmszNTY4LXJrbm4tY29yZSIpCj4gKwkJCWlmIChvZl9kZXZpY2VfaXNfYXZhaWxhYmxlKG4pKSB7 Cj4gKwkJCQlkbWFfYml0cyA9IDMyOwo+ICsJCQkJb2Zfbm9kZV9wdXQobik7Cj4gKwkJCQlicmVh azsKPiArCQkJfQo+ICsKPiArCQllcnIgPSBkbWFfc2V0X21hc2tfYW5kX2NvaGVyZW50KGRldiwg RE1BX0JJVF9NQVNLKGRtYV9iaXRzKSk7Cj4gKwkJaWYgKGVycikKPiArCQkJcmV0dXJuIEVSUl9Q VFIoZXJyKTsKPiArCX0KCgpIZWlrbwoKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpMaW51eC1yb2NrY2hpcCBtYWlsaW5nIGxpc3QKTGludXgtcm9ja2No aXBAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2xpbnV4LXJvY2tjaGlwCg==