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From: Dmitry Sinyavin <sinyavin@gmail.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Jassi Brar <jassisinghbrar@gmail.com>,
	Stephan Gerhold <stephan.gerhold@linaro.org>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: mailbox: qcom: Add MDM9607 APCS IPC
Date: Thu, 10 Sep 2026 13:23:02 +0200	[thread overview]
Message-ID: <51344c03-b651-40a1-8efb-f7e47c9f359c@gmail.com> (raw)
In-Reply-To: <47344b6d-d64c-43ef-9344-0409a434ee44@oss.qualcomm.com>

Hi Konrad,

Thanks for the review!

I based this on the downstream MDM9607 DT and clock driver (see 
https://android.googlesource.com/kernel/msm.git/+/android-7.1.0_r0.3/arch/arm/boot/dts/qcom/mdm9607.dtsi): 
the CPU mux/divider uses a separate register resource at 0x0b010008, and 
the APCS mailbox register is at 0x0b011008. But I see your point, I 
found SDX55 is using a layout very close to what you're proposing. That 
design might be superior indeed, although both would work. Let me think 
about it a bit more and come out with v2.

Best regards,
Dmitry


08.09.2026 13:02, Konrad Dybcio wrote:
> On 9/8/26 10:11 AM, Dmitry Sinyavin wrote:
>> The MDM9607 APCS IPC register is at offset 0x8 in the KPSS global block.
>> Its CPU clock controller is in a separate block, so the existing MSM8994
>> APCS match data can be used without registering a clock device.
> 
> Aren't you going to bind one to APCS though? IIRC the setup on MDM9607
> is somewhat similar to the one on 8916, although naturally a bit simpler.
> 
> +Stephan may know more
> 
> Konrad


      reply	other threads:[~2026-09-10 11:23 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08  8:11 [PATCH] dt-bindings: mailbox: qcom: Add MDM9607 APCS IPC Dmitry Sinyavin
2026-09-08 11:02 ` Konrad Dybcio
2026-09-10 11:23   ` Dmitry Sinyavin [this message]

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