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Date: Mon, 04 Mar 2013 18:31:44 +0100
From: Fabien Chouteau <chouteau@adacore.com>
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Subject: Re: [Qemu-devel] [PATCH 3/4] target-arm: Fix VFP register byte
 order in GDB remote
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To: Paul Brook <paul@codesourcery.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, afaerber@suse.de

On 03/04/2013 02:30 PM, Paul Brook wrote:
>>>> "The bytes with the register are transmitted in target byte order."
>>>>
>>>>          /* Aliases for Q regs.  */
>>>>          nregs += 16;
>>>>          if (reg < nregs) {
>>>>
>>>> -            stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
>>>> -            stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
>>>> +            stfq_p(buf, env->vfp.regs[(reg - 32) * 2]);
>>>> +            stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
>>>
>>> This is wrong. You're still using little-endian ordering of words.
>>
>> Can you explain a little bit further? If I'm in big-endian mode, stfq_p()
>> will be stfq_be_p(), right?
> 
> Because we're actually storing two halves of a 128-bit value.   You still 
> store the least significant half first.
> 

Right, I'm sorry I didn't see you comment was only about the Q registers.
What would be the solution then?

#ifdef TARGET_WORDS_BIGENDIAN
            stfq_p(buf, env->vfp.regs[(reg - 32) * 2 + 1]);
            stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2]);
#else
            stfq_p(buf, env->vfp.regs[(reg - 32) * 2]);
            stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
#endif  /* TARGET_WORDS_BIGENDIAN */

Regards,

-- 
Fabien Chouteau