Re: [Qemu-devel] [PATCH v2 0/3] Implement x86 soft reset

[Laszlo Ersek <lersek@redhat.com>]

On 03/05/13 20:00, Paolo Bonzini wrote:
> This series makes various devices (port 92h, pckbd and the
> PIIX4/ICH9 southbridges) implement x86 soft reset correctly.
> 
> v1->v2: rebased onto Andreas's branch, fixed target-ppc/cpu.h,
>         renamed function
> 
> Paolo Bonzini (3):
>   cpu: make CPU_INTERRUPT_RESET available on all targets
>   pc: port 92 reset requires a low->high transition
>   hw: correctly implement soft reset
> 
>  cpu-exec.c             | 24 ++++++++++++++----------
>  cpus.c                 |  9 +++++++++
>  hw/lpc_ich9.c          |  7 ++++++-
>  hw/pc.c                |  6 ++++--
>  hw/pckbd.c             |  5 +++--
>  hw/piix_pci.c          |  8 ++++++--
>  include/exec/cpu-all.h |  8 +++++---
>  include/sysemu/cpus.h  |  1 +
>  target-i386/cpu.h      |  7 ++++---
>  target-ppc/cpu.h       |  3 ---
>  10 files changed, 52 insertions(+), 26 deletions(-)
> 

You haven't addressed the difference on soft reset between
ich9_rst_cnt_write() and rcr_write() that I pointed out in v1 3/3, but I
can live with that.

Series
Reviewed-by: Laszlo Ersek <lersek@redhat.com>