From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UDA2Z-0008Qy-Aj for qemu-devel@nongnu.org; Wed, 06 Mar 2013 03:49:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UDA2Y-0006qu-9K for qemu-devel@nongnu.org; Wed, 06 Mar 2013 03:49:35 -0500 Received: from mail-gg0-x22d.google.com ([2607:f8b0:4002:c02::22d]:37944) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UDA2Y-0006qq-3t for qemu-devel@nongnu.org; Wed, 06 Mar 2013 03:49:34 -0500 Received: by mail-gg0-f173.google.com with SMTP id b6so1132524ggm.4 for ; Wed, 06 Mar 2013 00:49:33 -0800 (PST) Sender: Paolo Bonzini Message-ID: <51370317.2000709@redhat.com> Date: Wed, 06 Mar 2013 09:49:27 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1362510056-3316-1-git-send-email-pbonzini@redhat.com> <1362510056-3316-2-git-send-email-pbonzini@redhat.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 1/3] cpu: make CPU_INTERRUPT_RESET available on all targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: dwmw2@infradead.org, aliguori@us.ibm.com, lersek@redhat.com, qemu-devel@nongnu.org, afaerber@suse.de Il 06/03/2013 00:23, Peter Maydell ha scritto: > On 6 March 2013 03:00, Paolo Bonzini wrote: >> On the x86, some devices need access to the CPU reset pin (INIT#). >> Provide a generic service to do this, using one of the internal >> cpu_interrupt targets. Generalize the PPC-specific code for >> CPU_INTERRUPT_RESET to other targets, and provide a function that >> will raise the interrupt on all CPUs. > > Not sure this makes sense -- reset isn't an interrupt... cpu_interrupt is not just for interrupts, CPU_INTERRUPT_TGT_INT_* is a generic mechanism for adding events to the CPU that have to exit the translation block (they do not even have to be input pins, though CPU_INTERRUPT_RESET is). This patch just takes one particular CPU_INTERRUPT_TGT_INT_* value and makes it available to all targets. It is important for the reset to exit the translation block, or the CPU goes into the weeds. The problem I was seeing is that the code looked like: mov $0xfe, %al out %al, $0x60 jmp foo // this is a relative jump ... foo: cli hlt Now, if the reset were synchronous (i.e. cpu_reset), it would modify the stored PC to 0xfffffff0 without leaving the translation block. Because the jump is relative, it would go to 0xfffffff0 + the offset instead of jumping to foo. This could also be implemented by something like this: run_on_cpu(cpu, cpu_reset); cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); But I preferred to reuse the existing logic (there would be some additional complication because the x86 INIT signal does _not_ reset a couple of things that are reset at power up). Paolo