From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB Date: Fri, 08 Mar 2013 10:47:31 -0700 Message-ID: <513A2433.2080002@wwwdotorg.org> References: <1362751245-32432-1-git-send-email-ldewangan@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1362751245-32432-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Laxman Dewangan Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 03/08/2013 07:00 AM, Laxman Dewangan wrote: > UARTB clock bit in CAR register is 7. Correcting this > in DTS file. The register bit is 7, but the clock ID in the Tegra CAR DT binding is 96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and 2 separate IP block reset bits, or the other way around, so we highlight the issue by assigning different clock IDs. See the comment before the list of clock IDs in the binding document. From mboxrd@z Thu Jan 1 00:00:00 1970 From: swarren@wwwdotorg.org (Stephen Warren) Date: Fri, 08 Mar 2013 10:47:31 -0700 Subject: [PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB In-Reply-To: <1362751245-32432-1-git-send-email-ldewangan@nvidia.com> References: <1362751245-32432-1-git-send-email-ldewangan@nvidia.com> Message-ID: <513A2433.2080002@wwwdotorg.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 03/08/2013 07:00 AM, Laxman Dewangan wrote: > UARTB clock bit in CAR register is 7. Correcting this > in DTS file. The register bit is 7, but the clock ID in the Tegra CAR DT binding is 96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and 2 separate IP block reset bits, or the other way around, so we highlight the issue by assigning different clock IDs. See the comment before the list of clock IDs in the binding document. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934532Ab3CHRrg (ORCPT ); Fri, 8 Mar 2013 12:47:36 -0500 Received: from avon.wwwdotorg.org ([70.85.31.133]:58555 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933577Ab3CHRrf (ORCPT ); Fri, 8 Mar 2013 12:47:35 -0500 Message-ID: <513A2433.2080002@wwwdotorg.org> Date: Fri, 08 Mar 2013 10:47:31 -0700 From: Stephen Warren User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Laxman Dewangan CC: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB References: <1362751245-32432-1-git-send-email-ldewangan@nvidia.com> In-Reply-To: <1362751245-32432-1-git-send-email-ldewangan@nvidia.com> X-Enigmail-Version: 1.4.6 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/08/2013 07:00 AM, Laxman Dewangan wrote: > UARTB clock bit in CAR register is 7. Correcting this > in DTS file. The register bit is 7, but the clock ID in the Tegra CAR DT binding is 96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and 2 separate IP block reset bits, or the other way around, so we highlight the issue by assigning different clock IDs. See the comment before the list of clock IDs in the binding document.