From mboxrd@z Thu Jan 1 00:00:00 1970 From: Egger Christoph Subject: Re: [PATCH] x86/MCE: Present MSR_IA32_MCx_MISC(2-6) as invalid on AMD Date: Tue, 12 Mar 2013 16:43:15 +0100 Message-ID: <513F4D13.5060305@amazon.de> References: <1363102363-1719-1-git-send-email-boris.ostrovsky@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1363102363-1719-1-git-send-email-boris.ostrovsky@oracle.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Boris Ostrovsky Cc: bp@alien.de, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 12.03.13 16:32, Boris Ostrovsky wrote: > MSR_IA32_MCx_MISC(4) register on AMD processors is used for error > thresholding. PV guests may try to set it up for threshold > interrupts which will fail and result in these warnings in the log: > > [Firmware Bug]: cpu 0, try to use APIC510 (LVT offset 1) for vector > 0xf9, but the register is already in use for vector 0x0 on this cpu > > Mark this register as invalid to avoid this. While at it, also present > other MSR_IA32_MCx_MISC() registers as invalid (except for the first > GUEST_MC_BANK_NUM which are emulated). > > Signed-off-by: Boris Ostrovsky Acked-by: Christoph Egger > --- > xen/arch/x86/cpu/mcheck/mce.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h > index f2aeacb..d6526a4 100644 > --- a/xen/arch/x86/cpu/mcheck/mce.h > +++ b/xen/arch/x86/cpu/mcheck/mce.h > @@ -166,6 +166,7 @@ static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr) > case MSR_F10_MC4_MISC1: > case MSR_F10_MC4_MISC2: > case MSR_F10_MC4_MISC3: > + case MSR_IA32_MCx_MISC(GUEST_MC_BANK_NUM)...MSR_IA32_MCx_MISC(6): > return 1; > } > break; >