Re: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

[Vipul Pandya <vipul-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org>]

On 12-03-2013 20:12, Steve Wise wrote:
> On 3/12/2013 7:19 AM, David Miller wrote:
>> From: Vipul Pandya <vipul-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org>
>> Date: Tue, 12 Mar 2013 17:16:17 +0530
>>
>>> +				writel(n,  adap->bar2 + q->udb + 8);
>>> +#if defined(CONFIG_X86_32) || defined(CONFIG_X86_64)
>>> +			asm volatile("sfence" : : : "memory");
>>> +#endif
>> There is absolutely no way I'm letting anyone put crap like this
>> into a driver.
>>
>> Use a portable inteface, and if one does not exist create one.
> 
> I guess you'll have to add a wc_wmb() function for all the hw platforms 
> supported by the kernel.  I see libibverbs defines this for the user 
> side in include/infiniband/arch.h, and that could be used as the meat of 
> the hw platform-specific implementations.
> 
I see that normal wmb() code for x86_64 architecture is same as what
above #ifdef condition is doing. To be more clear I looked at the
assembly code for wmb and find that it is converted into 'sfence'
instruction. So, I think above code should be replaced with wmb call
which will also take care of portability on different architecture. I
will submit the series again soon.

I would like to request RDMA/cxgb4 and csiostor driver maintainer to
review the series if it has not been done already. It would be great If
I can include review comments from them in my next version of series.
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